LPC1343FHN33 NXP Semiconductors, LPC1343FHN33 Datasheet - Page 54

• Manufacturer Part Number: LPC1343FHN33
• Description: The LPC1343FHN33 is a ARM Cortex-M3 based microcontroller for embedded applications featuring a high level of integration and low power consumption
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 19.
[1]
[2]
[3]
[4]
LPC1311_13_42_43
Product data sheet
Symbol
SSP master
T
t
t
t
t
SSP slave
T
t
t
t
t
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
cy(clk)
cy(PCLK)
T
main clock frequency f
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
= 40 C to +85 C.
= 25 C; V
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
= 12  T
Dynamic characteristics: SSP pins in SPI mode
Parameter
clock cycle time
data set-up time
data hold time
data output valid time
data output hold time
PCLK cycle time
data set-up time
data hold time
data output valid time
data output hold time
10.7 SSP0/1 interface
cy(PCLK)
DD
= 3.3 V.
main
.
Remark: The SSP1 interface is available on the LPC1313FBD48/01 only.
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
Conditions
full-duplex mode
when only transmitting
in SPI mode;
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
2.4 V  V
2.0 V  V
All information provided in this document is subject to legal disclaimers.
main
DD
DD
Rev. 4 — 20 June 2011
. The clock cycle time derived from the SPI bit rate T
 3.6 V
< 2.4 V
[1]
[1]
[2]
[2]
[2]
[2]
[2]
[3][4]
[3][4]
[3][4]
[3][4]
Min
40
27.8
15
20
0
-
0
13.9
0
3  T
-
-
cy(PCLK)
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
+ 4
Max
-
-
-
-
-
10
-
-
-
-
3  T
2  T
cy(PCLK)
cy(PCLK)
cy(clk)
© NXP B.V. 2011. All rights reserved.
is a function of the
+ 11
+ 5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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