ST72344S4 STMicroelectronics, ST72344S4 Datasheet
ST72344S4
Specifications of ST72344S4
Related parts for ST72344S4
ST72344S4 Summary of contents
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... PWM and pulse generator modes 2 C multimaster / slave 2 C slave 3 addresses no stretch with DMA access and byte pair coherency on I²C Read compatible) pin devices) detection package Device summary Part numbers ST72344K2, ST72344K4, ST72344S2, ST72344S4 ST72345C4 LQFP44 10 × 1/247 www.st.com 1 ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72344xx ST72345xx 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 8.5.2 8.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72344xx ST72345xx 11.1.8 11.1.9 11.1.10 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 11.6 I2C bus interface (I2C ...
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ST72344xx ST72345xx 13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 15.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 ...
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ST72344xx ST72345xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72344xx ST72345xx Table 100. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72344xx ST72345xx Figure 48. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 100. Typical Figure 101. Typical Figure 102. Typical Figure 103. Typical Figure 104. Typical V at ...
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ST72344xx ST72345xx 1 Introduction The ST7234x devices are members of the ST7 microcontroller family. available part numbers and details on the devices. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. They feature single-voltage ...
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... RAM (stack) - bytes EEPROM data - bytes Common peripherals Other peripherals CPU frequency Temperature range Package 16/247 ST72344K2, ST72344K4, ST72344S2, ST72344S4 8K 16K 512 bytes (256 bytes) 1 Kbyte (256 bytes) 256 256 Window watchdog, 2 16-bit timers, SCI, SPI, I2CMMS 10-bit ADC 8 MHz @ 3 5 MHz @ 2 5.5 V -40 ° ...
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ST72344xx ST72345xx 2 Pin description Figure 2. LQFP32 package pinout OCMP1_A / AIN10 / PF4 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 DDA 1 ei3 ei2 V SSA 2 ...
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Pin description Figure 3. LQFP44 package pinout 18/247 RDI / PE1 ei0 1 PB0 2 PB1 3 ei0 ei2 PB2 4 PB3 5 (HS) PB4 6 ei3 AIN0 / ...
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ST72344xx ST72345xx Figure 4. LQFP48 package pinout Note: For external pin connection guidelines, refer to page 199 PE0/TD0 1 RDI / PE1 2 ei0 PB0 3 PB1 4 ...
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Pin description Legend / Abbreviations for Type: Input level: In/Output level: C Output level high sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu = weak pull-up, int = interrupt ● ...
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ST72344xx ST72345xx Table 3. Device pin description (continued) Pin n° Pin name PC2 (HS)/ICAP2_B PC3 (HS)/ICAP1_B PC4/MISO/ICCDATA PC5/MOSI/AIN14 PC6/SCK/ICCCLK PC7/SS/AIN15 16 31 ...
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Pin description Table 3. Device pin description (continued) Pin n° Pin name PE1/RDI PB0 ( PB1 ( PB2 PB3 PB4 (HS) 31 ...
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ST72344xx ST72345xx 3 Register and memory map As shown in Figure registers. The available memory locations consist of 128 bytes of register locations Kbytes of RAM, 256 bytes of Data EEPROM and Kbytes of ...
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Register and memory map Table 4. Hardware register map Register Address Block label 0000h PADR (3) 0001h Port A PADDR 0002h PAOR 0003h PBDR (3) 0004h Port B PBDDR 0005h PBOR 0006h PCDR (3) 0007h Port C PCDDR 0008h PCOR ...
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ST72344xx ST72345xx Table 4. Hardware register map (continued) Register Address Block label 0031h TACR2 0032h TACR1 0033h TACSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR ...
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Register and memory map Table 4. Hardware register map (continued) Register Address Block label 0060h I2C3SCR1 0061h I2C3SCR2 0062h I2C3SSR 0063h I2C3SBCR 0064h I2C3SSAR1 2 I C3SNS 0065h I2C3SCAR1 0066h I2C3SSAR2 0067h I2C3SCAR2 0068h I2C3SSAR3 0069h I2C3SCAR3 0070h ADCCSR 0071h ...
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ST72344xx ST72345xx 4 Flash program memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash ...
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Flash program memory 4.3.1 In-circuit programming (ICP) ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in ...
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ST72344xx ST72345xx isolate the application reset circuit in this case. When using a classical RC network with R> reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user ...
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Flash program memory In Flash devices, this protection is removed by reprogramming the option. In this case, both program and data E reprogrammed. Read-out protection selection depends on the device type: ● In Flash devices it is enabled and removed ...
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ST72344xx ST72345xx 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non-volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ● ...
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Data EEPROM Read operation (E2LAT = 0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, Data EEPROM can also be used to execute machine code. ...
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ST72344xx ST72345xx Figure 9. Data EEPROM write operation Row definition E2LAT bit E2PGM bit Note programming cycle is interrupted (by reset action), the integrity of the data in memory will not be guaranteed. 5.4 Power saving modes 5.4.1 ...
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Data EEPROM 5.6 Data EEPROM readout protection The readout protection is enabled through an option bit (see option byte section). When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out (including a ...
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ST72344xx ST72345xx 5.7 Register description 5.7.1 EEPROM control/status register (EECSR) Reset value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. ...
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Central processing unit 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 Main features ● Enable executing 63 basic instructions ● Fast 8-bit by ...
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ST72344xx ST72345xx Figure 11. CPU registers PCH 15 RESET VALUE = RESET VECTOR @ FFFEh-FFFFh RESET VALUE = 1 15 RESET VALUE = STACK HIGHER ADDRESS 6.3.1 Condition code register (CC) Reset value: 111x1xxx The 8-bit Condition ...
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Central processing unit Bit Negative. This bit is set and cleared by hardware representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7 0: The ...
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ST72344xx ST72345xx 6.3.2 Stack pointer (SP) Reset value: 01 FFh SP7 SP6 The Stack pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented after ...
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Central processing unit Figure 12. Stack manipulation example CALL Subroutine @ 0100h SP PCH @ 01FFh PCL Stack Higher Address = 01FFh Stack Lower Address = 0100h 40/247 PUSH Y Interrupt Event ...
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ST72344xx ST72345xx 7 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. 7.1 Main ...
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Supply, reset and clock management 7.2 Phase locked loop The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external clock obtain ...
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ST72344xx ST72345xx 7.3 Multioscillator (MO) The main clock of the ST7 can be generated by three different source types coming from the multioscillator block: ● an external source ● 4 crystal or ceramic resonator oscillators ● an internal high-accuracy RC ...
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Supply, reset and clock management Table 8. ST7 clock sources 44/247 Hardware configuration ST7 OSC1 OSC2 EXTERNAL SOURCE ST7 OSC1 OSC2 LOAD CAPACITORS ST7 OSC1 OSC2 Doc ID 12321 Rev 5 ST72344xx ST72345xx ...
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ST72344xx ST72345xx 7.3.3 Internal RC oscillator The device contains a high-precision internal RC oscillator. It must be calibrated to obtain the frequency required in the application. This is done by software writing a calibration value in the RCCRH and RCCRL ...
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Supply, reset and clock management 7.4.2 RC control register (RCCRL) Reset value: 0000 0011 (03h Bits 7:2 = Reserved, must be kept cleared. Bits 1:0 = CR[1:0] RC Oscillator Frequency Adjustment Bits This 10-bit value must be ...
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ST72344xx ST72345xx Figure 15. reset sequence phases 7.5.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input ...
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Supply, reset and clock management 7.5.4 Internal low-voltage detector (LVD) reset Two different reset sequences caused by the internal LVD circuitry can be distinguished: ● Power-on reset ● Voltage-drop reset The device RESET pin acts as an output that is ...
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ST72344xx ST72345xx 7.6.1 Low-voltage detector (LVD) The low-voltage detector function (LVD) generates a static reset when the V voltage is below a V the power-down keeping the ST7 in reset. The V reference value for a voltage drop is lower ...
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Supply, reset and clock management In the case of a drop in voltage below V is issued rises above the V DD hardware. No interrupt is generated, and therefore software should poll the AVDF bit to detect when ...
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ST72344xx ST72345xx 7.6.5 Register description System integrity (SI) control/status register (SICSR) Reset value: 000x 000x (xxh PDVDIE Bit 7 = Reserved, must be kept cleared. Bit 6 = AVDIE Voltage detector interrupt enable This bit is set and ...
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Supply, reset and clock management Application notes The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can ...
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ST72344xx ST72345xx 8 Interrupts 8.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software ...
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Interrupts Table 13. Interrupt software priority levels Interrupt software priority Level 3 (= interrupt disable) Figure 20. Interrupt processing flowchart RESET RESTORE PC FROM STACK Servicing pending interrupts As several interrupts can be pending at the same ...
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ST72344xx ST72345xx When an interrupt request is not serviced immediately latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one ...
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Interrupts 8.3 Interrupts and low-power modes All interrupts allow the processor to exit the Wait low-power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column “Exit from Halt” ...
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ST72344xx ST72345xx Figure 23. Nested interrupt management RIM MAIN 8.5 Interrupt register description 8.5.1 CPU CC register interrupt bits Reset value: 111x 1010 (xAh Bits I1, I0 Software interrupt priority These ...
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Interrupts 8.5.2 Interrupt software priority registers (ISPRX) Reset value: 1111 1111 (FFh) ISPR0 ISPR1 ISPR2 ISPR3 These four registers contain the interrupt software priority of each interrupt vector. ● Each interrupt vector (except reset and TRAP) has corresponding bits in ...
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ST72344xx ST72345xx Table 16. Dedicated interrupt instruction set (continued) Instruction RIM Enable interrupt (level 0 set) SIM Disable interrupt (level 3 set) TRAP Software trap WFI Wait for interrupt Note: During the execution of an interrupt routine, the HALT, POPCC, ...
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Interrupts 8.6 External interrupts 8.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 24). This control allows to have fully independent external interrupt ...
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ST72344xx ST72345xx 8.7 External interrupt control register (EICR) Reset value: 0000 0000 (00h) 7 IS11 IS10 Bits 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: ● ...
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Interrupts Bits 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: ● ei0 (port A3, port E1) Table 20. External interrupt sensitivity (ei0) IS21 IS20 0 0 ...
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ST72344xx ST72345xx Table 22. Nested interrupts register map and reset values Address Register (Hex.) label 0024h ISPR0 Reset value 0025h ISPR1 Reset value 0026h ISPR2 Reset value 0027h ISPR3 Reset value EICR 0028h Reset value ei1 ...
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Power-saving modes 9 Power-saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-Wait) ● ...
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ST72344xx ST72345xx 9.2 Slow mode This mode has two targets: ● To reduce power consumption by decreasing the internal clock in the device, ● To adapt the internal clock frequency (f Slow mode is controlled by three bits in the ...
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Power-saving modes Figure 27. Wait mode flowchart Note: 1 Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine ...
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ST72344xx ST72345xx system is enabled, can generate a Watchdog reset (see details). Figure 28. Halt timing overview Figure 29. Halt mode flowchart Note: 1 WDGHALT is an option bit. See option byte section for more details. 2 Peripheral clocked with ...
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Power-saving modes Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up ...
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ST72344xx ST72345xx Note: As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a reset. This means that the device cannot spend more than a defined delay in this power saving ...
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Power-saving modes 9.6 Auto-wakeup from Halt mode Auto-wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of an internal RC oscillator for wake-up. Compared to Active-Halt mode, AWUFH has lower power consumption because the main clock ...
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ST72344xx ST72345xx Figure 33. AWUF Halt timing diagram Run mode f CPU f AWU_RC AWUFH interrupt Figure 34. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external ...
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Power-saving modes 9.7 Register description 9.7.1 AWUFH control/status register (AWUCSR) Reset value: 0000 0000 (00h Bits 7:3 = Reserved. Bit 2= AWUF Auto-wakeup flag This bit is set by hardware when the AWU module generates an interrupt ...
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ST72344xx ST72345xx 9.7.2 AWUFH prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 AWUPR7 AWUPR6 Bits 7:0= AWUPR[7:0] Auto-wakeup Prescaler These 8 bits define the AWUPR Dividing factor (as explained below: Table 24. AWUPR dividing factor AWUPR[7:0 00h 01h ... ...
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I/O ports 10 I/O ports 10.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An ...
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ST72344xx ST72345xx Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity ...
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I/O ports Figure 35. I/O port general block diagram REGISTER ACCESS DR DDR OR OR SEL DDR SEL DR SEL EXTERNAL INTERRUPT SOURCE ( Table 27. I/O Port mode options Configuration mode Floating with/without Interrupt Input Pull-up with/without ...
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ST72344xx ST72345xx Table 28. I/O port configurations NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD 1. When the I/O port is in ...
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I/O ports It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. Warning: 10.3 ...
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ST72344xx ST72345xx 10.5.1 I/O port implementation The I/O port register configurations are summarized as follows. Standard ports: PA[5:4], PC[7:0], PD[5:0], PE0, PF[7:6], PF4 Table 31. I/O port register configurations (standard ports) floating input pull-up input open drain output push-pull output ...
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I/O ports Table 35. Port configuration Port Pin name PA7:6 Port A PA5:4 PA3 PB3 Port B PB4, PB2:0 Port C PC7:0 PD7:6 Port D PD5:0 PE1 Port E PE0 PF7:6, 4 Port F PF2 PF1:0 Caution: In small packages, ...
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ST72344xx ST72345xx Table 36. I/O port register map and reset values (continued) Address Register (Hex.) label 000Ch PEDR 000Dh PEDDR 000Eh PEOR 000Fh PFDR 0010h PFDDR 0011h PFOR MSB MSB Doc ID 12321 Rev 5 I/O ...
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On-chip peripherals 11 On-chip peripherals 11.1 Window watchdog (WWDG) 11.1.1 Introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to ...
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ST72344xx ST72345xx Figure 37. Watchdog block diagram RESET f OSC2 The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is ...
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On-chip peripherals Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). ● Watchdog reset on Halt option If the watchdog is activated and the watchdog reset ...
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ST72344xx ST72345xx Figure 39. Exact timeout duration (t Where (LSB + 128 min0 t = 16384 x t max0 t = 125 OSC2 CNT = Value of T[5:0] bits in the ...
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On-chip peripherals Figure 40. Window watchdog timing diagram WDGWR 11.1.6 Low-power modes Table 37. Descriptions Mode Slow No effect on Watchdog: The downcounter continues to decrement at normal speed. Wait No effect on Watchdog: The downcounter continues to decrement. OIE ...
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ST72344xx ST72345xx 11.1.7 Hardware watchdog option If hardware watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description. 11.1.8 Using Halt mode with ...
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On-chip peripherals Table 38. Watchdog timer register map and reset values Address Register (Hex.) label WDGCR 2A Reset value WDGWR 30 Reset value 11.2 Main clock controller with real-time clock and beeper (MCC/RTC) The main clock controller consists of three ...
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ST72344xx ST72345xx Figure 41. Main clock controller (MCC/RTC) block diagram MCCBCR f OSC2 11.2.5 Low-power modes Table 39. Mode description Mode No effect on MCC/RTC peripheral. Wait MCC/RTC interrupt cause the device to exit from Wait mode. No effect on ...
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On-chip peripherals 11.2.7 Register description MCC control/status register (MCCSR) Reset value: 0000 0000 (00h) 7 MCO CP1 Bit 7 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port set ...
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ST72344xx ST72345xx Table 42. Time base control Counter prescaler 16000 32000 80000 200000 A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows ...
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On-chip peripherals Table 43. Beep control BC1 The beep output signal is available in Active-halt mode but has to be disabled to reduce the consumption. Table 44. Main clock controller register map and reset values Address ...
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ST72344xx ST72345xx 11.3 16-bit timer 11.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input ...
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On-chip peripherals 11.3.3 Functional description Counter The main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register ...
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ST72344xx ST72345xx Figure 42. Timer block diagram f CPU EXEDG 1/2 1/4 1/8 EXTCLK pin CC[1:0] ICF1 OCF1 TOF ICIE OCIE TOIE (See note 1) TIMER INTERRUPT 1. If IC, OC and TO interrupt requests have separate vectors then the ...
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On-chip peripherals Figure 43. 16-bit read sequence (from either the counter register or the alternate counter register) The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the ...
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ST72344xx ST72345xx A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure ...
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On-chip peripherals Input capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two input-capture 16-bit registers (IC1R and IC2R) are used to latch the value ...
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ST72344xx ST72345xx Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set. ...
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On-chip peripherals When a match is found between the Output Compare register and the free running counter, the output compare function: ● Assigns pins with a programmable value if the OCIE bit is set ● Sets a flag in the ...
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ST72344xx ST72345xx Where: Δ ● Output compare period (in seconds) ● External timer clock frequency (in Hertz) EXT Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR ...
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On-chip peripherals Figure 49. Output compare block diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1R Register OC2R Register Figure 50. Output compare timing diagram, f OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) ...
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ST72344xx ST72345xx One-pulse mode One-pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one-pulse mode uses the Input Capture1 function and the Output ...
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On-chip peripherals The OC1R register value required for a specific timing application can be calculated using the following formula: Where: ● Pulse period (in seconds) ● CPU clock frequency (in Hertz) CPU ● = Timer prescaler ...
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ST72344xx ST72345xx Figure 54. Pulse width modulation mode timing example COUNTER 34E2 OCMP1 1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 Pulse-width modulation mode Pulse-width modulation (PWM) mode enables the generation of a signal with ...
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On-chip peripherals Figure 55. Pulse width modulation cycle If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The ...
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ST72344xx ST72345xx 11.3.4 Low-power modes Table 47. Low-power mode description Mode No effect on 16-bit timer. Wait Timer interrupts cause the Device to exit from Wait mode. 16-bit timer registers are frozen. In Halt mode, the counter stops counting until ...
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On-chip peripherals 11.3.6 Summary of timer modes Table 49. Timer modes Modes Input Capture 1 Input Capture (1 and/or 2) Output Compare (1 and/or 2) One-pulse mode PWM mode 1. See note 4 in One-pulse mode on page 103 2. ...
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ST72344xx ST72345xx Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is ...
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On-chip peripherals length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 50. Clock control ...
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ST72344xx ST72345xx Bit 5 = TOF Timer Overflow Flag timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the ...
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On-chip peripherals Output compare 1 high register (OC1HR) Read/Write Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Output compare 1 low ...
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ST72344xx ST72345xx Counter low register (CLR) Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing ...
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On-chip peripherals Table 51. 16-bit timer register map and reset values Address Register (Hex.) label Timer A: 32 CR1 Timer B: 42 Reset value Timer A: 31 CR2 Timer B: 41 Reset value Timer A: 33 CSR Timer B: 43 ...
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ST72344xx ST72345xx 11.4 Serial peripheral interface (SPI) 11.4.1 Introduction The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which ...
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On-chip peripherals Figure 56. Serial peripheral interface block diagram MOSI MISO SOD bit SCK SS Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure The MOSI pins are connected together ...
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ST72344xx ST72345xx Figure 57. Single master/ single slave application MASTER MSBit 8-bit SHIFT REGISTER SPI CLOCK GENERATOR Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage ...
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On-chip peripherals Figure 58. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA = 0) Figure 59. Hardware/software slave select management Master mode operation In master mode, the serial clock is output on the SCK pin. The clock ...
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ST72344xx ST72345xx Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is ...
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On-chip peripherals Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the ...
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ST72344xx ST72345xx Figure 60. Data clock timing diagram SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MOSI (from ...
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On-chip peripherals Clearing the MODF bit is done through a software sequence read access to the SPICSR register while the MODF bit is set write to the SPICR register. Notes: To avoid any conflicts in an ...
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ST72344xx ST72345xx Figure 61. Clearing the WCOL bit (write collision flag) software sequence 1st Step 2nd Step 1. Writing to the SPIDR register instead of reading it does not reset the WCOL bit. Single master and multimaster configurations There are ...
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On-chip peripherals Figure 62. Single master / multiple slave configuration SCK Slave Device MOSI MOSI SCK Master Device 5V SS 11.4.6 Low-power modes Table 52. Description Mode No effect on SPI. Wait SPI interrupt events cause the device to exit ...
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ST72344xx ST72345xx 11.4.7 Interrupts Table 53. Interrupt events Interrupt event SPI end of transfer event Master mode fault event Overrun error Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt ...
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On-chip peripherals Bit 4 = MSTR Master Mode This bit is set and cleared by software also cleared by hardware when, in master mode (see 0: Slave mode 1: Master mode. The function of the ...
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ST72344xx ST72345xx Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read-only) This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register cleared by ...
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On-chip peripherals SPI data I/O register (SPIDR) Reset value: Undefined The SPIDR register is used to transmit and receive data on the serial bus master device, a write to this register will initiate transmission/reception of ...
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ST72344xx ST72345xx 11.5 SCI serial communication interface 11.5.1 Introduction The serial communications interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide ...
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On-chip peripherals peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity are software programmable. ● TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter ...
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ST72344xx ST72345xx Figure 63. SCI block diagram TDO RDI SCICR2 TIE TRANSMITTER Write Transmit Data Register (TDR) Transmit Shift Register R8 T8 WAKE TRANSMIT UP CONTROL UNIT TCIE RIE ILIE TE RE RWU SBK SCI INTERRUPT CONTROL CLOCK f CPU ...
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On-chip peripherals 11.5.4 Functional description The block diagram of the Serial Control Interface, is shown in dedicated registers: ● 2 control registers (SCICR1 and SCICR2) ● A status register (SCISR) ● A baud rate register (SCIBRR) ● An extended prescaler ...
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ST72344xx ST72345xx Figure 64. Word length programming 9-bit (M bit is set) Start Bit0 Bit CLOCK 8-bit (M bit is reset) Start Bit CLOCK 1. LBCL bit controls last data clock pulse. Transmitter The transmitter can send data words of ...
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On-chip peripherals Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see ...
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ST72344xx ST72345xx Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the ...
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On-chip peripherals Overrun error An overrun error occurs when a character is received when RDRF has not been reset. Data cannot be transferred from the shift register to the RDR register until the RDRF bit is cleared. When a overrun ...
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ST72344xx ST72345xx Framing error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. – A break is received. When the framing error is ...
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On-chip peripherals Conventional baud rate generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows CPU Tx = (16 PR with ...
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ST72344xx ST72345xx Setting the RWU bit by software puts the SCI in sleep mode: ● None of the reception status bits can be set. ● All the receive interrupts are inhibited. A muted receiver can be woken up in one ...
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On-chip peripherals SCI clock tolerance During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the ...
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ST72344xx ST72345xx after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered detected as a “1”. – During sampling of the 16 samples, if one of the ...
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On-chip peripherals 11.5.6 Interrupts Table 58. Interrupt events Interrupt event Transmit data register empty Transmission complete Received data ready to be read Overrun error detected Idle line detected Parity error The SCI interrupt events are connected to the same interrupt ...
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ST72344xx ST72345xx cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line ...
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On-chip peripherals Control register 1 (SCICR1) Reset value: x000 0000 (x0h Bit Receive data bit 8. This bit is used to store the 9th bit of the received word when Bit ...
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ST72344xx ST72345xx Bit 0 = PIE Parity interrupt enable. This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set set and cleared by software. 0: Parity error interrupt ...
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On-chip peripherals Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: ...
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ST72344xx ST72345xx Table 59. SCP[1:0] configuration PR prescaling factor Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to the bus clock to yield the ...
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On-chip peripherals Note: This RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise replaced by the (RR*ERPR) dividing factor. Extended receive prescaler division register (SCIERPR) Reset value: 0000 0000 (00h) 7 ...
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ST72344xx ST72345xx Table 63. SCI register map and reset values Address Register 7 (Hex.) Label SCISR TDRE 0050h Reset value 1 SCIDR MSB 0051h Reset value x SCIBRR SCP1 0052h Reset value 0 SCICR1 R8 0053h Reset value x SCICR2 ...
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On-chip peripherals 2 11 bus interface (I2C) 11.6.1 Introduction 2 The I C bus interface serves as an interface between the microcontroller and the serial I bus. It provides both multimaster and slave functions, and controls all I ...
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ST72344xx ST72345xx Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition ...
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On-chip peripherals 2 When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. 2 When the I ...
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ST72344xx ST72345xx Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: ● Acknowledge pulse if the ACK bit is set. ● EVF and ADSL bits are set with an ...
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On-chip peripherals new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. Note: In ...
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ST72344xx ST72345xx Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master receiver Following the address transmission and ...
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On-chip peripherals master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set. ● AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits ...
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ST72344xx ST72345xx Figure 69. Transfer sequencing 7-bit Slave receiver: S Address A EV1 7-bit Slave transmitter: S Address A EV1 EV3 7-bit Master receiver: S Address A EV5 7-bit Master transmitter: S Address A EV5 10-bit Slave receiver: S Header ...
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On-chip peripherals EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by ...
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ST72344xx ST72345xx 2 1. The I C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset ...
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On-chip peripherals Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software also cleared by hardware when the interface is disabled (PE=0 acknowledge returned 1: Acknowledge returned after an address byte or ...
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ST72344xx ST72345xx Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs cleared by software reading SR2 register in case of error event or as described in hardware when the ...
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On-chip peripherals Figure 69). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. ● Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is ...
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ST72344xx ST72345xx Bit Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE= cleared by software reading SR2 register or by hardware when the interface is ...
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On-chip peripherals clock control register (CCR) Reset value: 0000 0000 (00h) 7 FM/SM CC6 Bit 7 = FM/SM Fast/Standard I This bit is set and cleared by software not cleared when the interface is disabled ...
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ST72344xx ST72345xx data register (DR) Reset value: 0000 0000 (00h Bits 7:0 = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. ● Transmitter mode: byte ...
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On-chip peripherals own address register (OAR2) Reset value: 0100 0000 (40h) 7 FR1 FR0 Bit 7:6 = FR[1:0] Frequency bits. These bits are set by software only when the interface is disabled (PE=0). To configure the interface ...
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ST72344xx ST72345xx 11.7 I2C triple slave interface with DMA (I2C3S) 11.7.1 Introduction 2 The I C3S interface provides three I2C slave functions, supporting both standard (up to 100 kHz) and fast I ● Full-speed emulation of standard I ● Receiving ...
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On-chip peripherals 2 Figure 71. I C3S interface block diagram SDA or SDAI SCL or SCLI 11.7.3 General description In addition to receiving and transmitting data, I2C3S converts it from serial to parallel format and vice versa. The interrupts are ...
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ST72344xx ST72345xx SDA/SCL line control When the I2C3S interface is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C3S ...
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On-chip peripherals The Byte count register is reset when it reaches 256 bytes, whatever the page length, for all slave addresses, including slave 3. DMA 2 The I C slaves use a DMA controller to write/read data to/from their RAM ...
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ST72344xx ST72345xx Word mode is disabled by hardware after the word update is performed. It must be enabled before each word update by CPU. Use the following procedure when the ST7 writes a word in RAM: 1. Disable interrupts 2. ...
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On-chip peripherals Figure 74. 16-bit word read operation flowchart Host Sends address and read bit Sends read address Repeat Receives byte 1 Receives byte 2 Stop condition Byte-Pair Coherency ensured by setting Word Mode + DMA on Words RAM start ...
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ST72344xx ST72345xx Address matched: the interface generates in sequence the following: ● An Acknowledge pulse ● Depending on the LSB of the slave address sent by the master, slaves enter transmitter or receiver mode. ● Send an interrupt to the ...
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On-chip peripherals When the memory address limit is reached the current address will roll over and the sequential read will continue till the addressing master sends a stop condition. Refer to Figure 81 Combined format If a master wants to ...
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ST72344xx ST72345xx Figure 75. Transfer sequencing 7-bit Slave receiver: S Address A 7-bit Slave transmitter: S Address A Legend Start Stop Acknowledge Non-acknowledge event, WFx bit is set (with ...
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On-chip peripherals Figure 80. Random read (dummy write + stop + start + current address read) Start SA Figure 81. Sequential read Start SA Figure 82. Combined format for read Start SA Legend Slave Address Byte ...
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ST72344xx ST72345xx 11.7.7 Interrupt generation Figure 83. Event flags and interrupt generation Restart Stop Dummy Write Write Protect RF1 RF2 ITRE1/2 NACK BERR WF1 WF2 ITWE1/2 WF3 ITWE3 BERR NACK RF3 ITRE3 Note: Read/Write interrupts are generated only after stop ...
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On-chip peripherals 11.7.8 Register description control register 1 (I2C3SCR1) Reset value: 0000 0000 (00h) 7 PL1 PL0 Bits 7:6 = PL1:0 Page length configuration This bit is set and cleared by software also cleared ...
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ST72344xx ST72345xx Bit 1= ITWE3 Interrupt enable on write to Slave 3 This bit is set and cleared by software also cleared by hardware when interface is disabled. 0: Interrupt after write to Slave 3 disabled 1: Interrupt ...
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On-chip peripherals Bit 1 = BusyW Busy on Write to RAM Buffer This bit is set by hardware when a Stop/ Restart is detected after a write operation. The I2C3S peripheral is temporarily disabled till this bit is reset. This ...
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ST72344xx ST72345xx Bit 4 = WF2 Write operation to Slave 2 This bit is set by hardware on reception of the direction bit in the I Slave 2. This bit is cleared when the status register is read when there ...
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On-chip peripherals I2C slave 1 address register (I2C3SSAR1) Reset value: 0000 0000 (00h) 7 ADDR7 ADDR6 Bits 7:1 = ADDR[7:1] Address of Slave 1 This register contains the first 7 bits of Slave 1 address (excluding the LSB) and is ...
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ST72344xx ST72345xx I2C slave 1 memory current address register (I2C3SCAR1) Reset value: 0000 0000 (00h) 7 CA7 CA6 Bit 7:0 = CA[7:0] Current address of Slave 1 buffer This register contains the 8 bit offset of Slave Address 1 reserved ...
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On-chip peripherals 2 Table 71. I C3S register map (continued) Address Register (Hex.) name 0066h I2C3SSAR2 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 0067h I2C3SCAR2 0068h I2C3SSAR3 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 0069h I2C3SCAR3 184/247 ...
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ST72344xx ST72345xx 11.8 10-bit A/D converter (ADC) 11.8.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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On-chip peripherals 11.8.3 Functional description The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V conversion result is FFh in ...
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ST72344xx ST72345xx Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the ...
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On-chip peripherals Bits 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. Table 73. Channel selection Channel pin AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 Reserved Reserved AIN8 Reserved AIN10 ...
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ST72344xx ST72345xx Table 74. ADC register map and reset values Address Register (Hex.) label ADCCSR 0070h Reset value ADCDRH 0071h Reset value ADCDRL 0072h Reset value EOC SPEED ADON ...
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Instruction set 12 Instruction set 12.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Table 75. Addressing mode groups Addressing mode The ST7 Instruction set is designed to minimize ...
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ST72344xx ST72345xx Table 76. ST7 addressing mode overview (continued) Mode Short Indirect Indexed ld A,([$10],X) Long Indirect Indexed ld A,([$10.w],X) Relative Direct jrne loop Relative Indirect jrne [$10] Bit Direct bset $10,#7 Bit Indirect bset [$10],#7 Bit Direct Relative btjt ...
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Instruction set Table 77. Inherent instructions (continued) Inherent instruction SLL, SRL, SRA, RLC, RRC SWAP 12.1.2 Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Table 78. Immediate instructions Immediate ...
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ST72344xx ST72345xx Indexed (No offset) There is no offset (no extra byte after the opcode), and allows addressing space. ● Indexed (Short) The offset is a byte, thus requires only 1 byte after the opcode and allows ...
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Instruction set Table 79. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Long and short instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Table 80. Short instructions Short instructions only CLR INC, DEC TNZ CPL, ...
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ST72344xx ST72345xx 12.2 Instruction groups The ST7 family devices use an instruction set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 82. Main instruction groups Load and Transfer ...
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Instruction set 12.2.1 Illegal opcode reset In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented code to be executed does not correspond to any opcode or prebyte ...
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ST72344xx ST72345xx Table 83. Illegal opcode detection (continued) Mnemo Description JRM Jump JRNM Jump JRMI Jump (minus JRPL Jump (plus) ...
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Instruction set Table 83. Illegal opcode detection (continued) Mnemo Description SUB Subtraction SWAP SWAP nibbles TNZ Test for Neg & Zero TRAP S/W trap WFI Wait for Interrupt XOR Exclusive OR 198/247 Function/Example Dst ...
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ST72344xx ST72345xx 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 13.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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Electrical characteristics 13.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 86. Pin input voltage 13.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage ...