ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 162

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
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Bit 2 = ADSL Address matched (Slave mode).
Bit 1 = M/SL Master/Slave.
Bit 0 = SB Start bit (Master mode).
I
Reset value: 0000 0000 (00h)
Bit 7:5 = Reserved.
2
C status register 2 (SR2)
Figure
DR register.
Following a byte reception, this bit is set after transmission of the acknowledge clock
pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte
from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if ITE=1.
It is cleared by software reading SR1 register or by hardware when the interface is
disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1
register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
Forced to 0 by hardware.
7
0
69). BTF is cleared by reading SR1 register followed by writing the next byte in
0
0
Doc ID 12321 Rev 5
AF
Read Only
STOPF
ARLO
ST72344xx ST72345xx
BERR
GCAL
0