ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 159

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
11.6.7
Note:
Note:
1. The I
Register description
I
Reset value: 0000 0000 (00h)
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I
activates the interface (only PE is set).
Bit 4 = ENGC Enable General Call.
In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition.
●
●
2
C control register (CR)
generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset
(RIM instruction).
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0) or when the Start condition is sent (with interrupt generation if
ITE=1).
In master mode:
0: No start generation
1: Repeated start generation
In slave mode:
0: No start generation
1: Start generation when the bus is free
7
0
2
C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They
2
C interface, write the CR register TWICE with PE=1 as the first write only
0
PE
Doc ID 12321 Rev 5
ENGC
Read / Write
START
ACK
On-chip peripherals
STOP
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ITE
0