ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 146

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
Note:
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Bit 1 = RWU Receiver wake-up.
Before selecting Mute mode (by setting the RWU bit) the SCI must first receive a data byte,
otherwise it cannot function in Mute mode with wake-up by Idle line detection.
In Address Mark Detection Wake-Up configuration (WAKE bit = 1) the RWU bit cannot be
modified by software while the RDRF bit is set.
Bit 0 = SBK Send break.
If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of
the current word.
Data register (SCIDR)
Reset value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from
or written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
Baud rate register (SCIBRR)
Reset value: 0000 0000 (00h)
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges as shown in
SCP1
DR7
This bit determines if the SCI is in mute mode or not. It is set and cleared by software
and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in active mode
1: Receiver in mute mode
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
7
7
SCP0
DR6
Figure
Figure
63).
63).
SCT2
DR5
Doc ID 12321 Rev 5
SCT1
DR4
Read/Write
Read/Write
SCT0
DR3
SCR2
DR2
ST72344xx ST72345xx
SCR1
DR1
Figure
SCR0
DR0
0
0
59.