ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 117

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
12.4
12.5
1
2
3
4
5
f
The Output Compare 2 event causes the counter to be initialized to FFFCh (See
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
Low power modes
Table 47.
Interrupts
Table 48.
EXT
WAIT
HALT
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Mode
=
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes
from the previous count when the MCU is woken up by an interrupt with “exit from HALT
mode” capability or from the counter reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT
mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT
mode is captured into the ICiR register.
Effect of low power modes on 16-bit timer
Timer interrupt control and wake-up capability
External timer clock frequency (in hertz)
Interrupt event
Doc ID 12370 Rev 8
Description
Event
OCF1
OCF2
ICF1
ICF2
TOF
flag
control
Enable
OCIE
TOIE
ICIE
bit
from
wait
Exit
Yes
16-bit timer
Figure
117/324
from
Exit
halt
No
58)