ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 261

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
18.3.3
18.3.4
18.4
Note:
18.5
18.6
18.6.1
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
ADCDR consistency
If an End Of Conversion event occurs after software has read the ADCDRLSB but before it
has read the ADCDRMSB, there would be a risk that the two values read would belong to
different samples.
To guarantee consistency:
●
●
This is important, as the ADCDR register will not be updated until the ADCDRH register is
read.
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 90.
Interrupts
None.
Register description
Control/status register (ADCCSR)
Read/ write (except bit 7 read only)
Reset value: 0000 0000 (00h)
WAIT
HALT
EOC
The ADCDRL and the ADCDRH registers are locked when the ADCCRL is read
The ADCDRL and the ADCDRH registers are unlocked when the ADCDRH register is
read or when ADON is reset.
7
Mode
Effect of low power modes on ADC
SPEED
No effect on A/D converter
A/D converter disabled.
After wakeup from Halt mode, the A/D converter requires a stabilization time
t
performed.
STAB
(see Electrical Characteristics) before accurate conversions can be
ADON
Doc ID 12370 Rev 8
SLOW
Description
CH3
CH2
10-bit A/D converter (ADC)
CH1
261/324
CH0
0