ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 147

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
14.3.2
Figure 71. Single master/ single slave application
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
●
In Slave Mode:
There are two cases depending on the data/clock timing relationship (see
If CPHA = 1 (data latched on second clock edge):
●
If CPHA = 0 (data latched on first clock edge):
●
Figure 72. Generic SS timing diagram
SS internal must be held high continuously
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to V
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
Collision error will occur when the slave writes to the shift register (see
error
(WCOL)).
MOSI/MISO
Master SS
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
MASTER
Figure
LSBit
Doc ID 12370 Rev 8
73).
Byte 1
SCK
MOSI
MISO
SS
+5V
MOSI
MISO
SCK
SS
Byte 2
SS
Serial peripheral interface (SPI)
, or made free for standard I/O by
8-BIT SHIFT REGISTER
MSBit
Not used if SS is managed
by software
Byte 3
SLAVE
Figure
Write collision
LSBit
72):
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