ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 203

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
16.4.5
Note:
16.4.6
RR = 1, 2, 4, 8, 16, 32, 64, 128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example 1: If f
and receive baud rates are 38400 baud.
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional baud rate generator retains industry standard software
compatibility.
The extended baud rate generator block diagram is described in the
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
with:
ETPR = 1...255 (see SCIETPR register)
ERPR = 1...255 (see SCIERPR register)
Receiver muting and wake-up feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non addressed receivers.
The non addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the following two ways:
●
●
Receiver wakes-up by idle line detection when the receive line has recognized an idle frame.
Then the RWU bit is reset by hardware but the IDLE bit is not set.
By idle line detection if the WAKE bit is reset,
By address mark detection if the WAKE bit is set.
CPU
is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit
Tx =
16
Doc ID 12370 Rev 8
LINSCI serial communication interface (LIN master only)
*
ETPR*(PR*TR)
f
CPU
Rx =
16
*
ERPR*(PR*RR)
f
CPU
Figure
90.
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