ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 175

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
15.8.7
Note:
15.9
15.9.1
Extended transmit prescaler division register (SCIETPR)
Read/ write
Reset value: 0000 0000 (00h)
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register.
The extended baud rate generator is activated when a value other than 00h is stored in this
register. The clock frequency from the 16 divider (see
factor set in the SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
In LIN slave mode, the conventional and extended baud rate generators are disabled.
LIN mode - functional description.
The block diagram of the Serial Control Interface, in LIN slave mode is shown in
It uses six registers:
●
●
●
The bits dedicated to LIN are located in the SCICR3. Refer to the register descriptions in
Section 15.10: LIN mode register
Entering LIN mode
To use the LINSCI in LIN mode the following configuration must be set in SCICR3 register:
●
●
Master
To enter master mode the LSLV bit must be reset In this case, setting the SBK bit will send
13 low bits.
Then the baud rate can programmed using the SCIBRR, SCIERPR and SCIETPR registers.
In LIN master mode, the conventional and/ or extended prescaler define the baud rate (as in
standard SCI mode)
Slave
Set the LSLV bit in the SCICR3 register to enter LIN slave mode. In this case, setting the
SBK bit will have no effect.
ETPR7
3 control registers: SCICR1, SCICR2 and SCICR3
2 status registers: the SCISR register and the LHLR register mapped at the SCIERPR
address
A baud rate register: LPR mapped at the SCIBRR address and an associated fraction
register LPFR mapped at the SCIETPR address
Clear the M bit to configure 8-bit word length.
Set the LINE bit.
7
ETPR6
ETPR5
LINSCI serial communication interface (LIN master/slave)
Doc ID 12370 Rev 8
descriptionfor the definitions of each bit.
ETPR4
ETPR3
Figure
ETPR2
79) is divided by the binary
ETPR1
Figure
ETPR0
175/324
0
81.