ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 242

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

beCAN controller (beCAN)
CAN receive FIFO registers (CRFR)
Note:
Note:
242/324
Read / write
Reset value: 0000 0000 (00h)
To clear a bit in this register, software must write a “1” to the bit.
Bits 7:6 = reserved. Forced to 0 by hardware.
Bit 5 = RFOM Release FIFO Output Mailbox
Read/Set
Set by software to release the output mailbox of the FIFO. The output mailbox can only be
released when at least one message is pending in the FIFO. Setting this bit when the FIFO
is empty has no effect. If more than one message are pending in the FIFO, the software has
to release the output mailbox to access the next message.
Cleared by hardware when the output mailbox has been released.
Bit 4 = FOVR FIFO Overrun
Read/ clear
This bit is set by hardware when a new message has been received and passed the filter
while the FIFO was full.
This bit is cleared by software.
Bit 3 = FULL FIFO Full
Read/ clear
Set by hardware when three messages are stored in the FIFO.
This bit can be cleared by software writing a one to this bit or releasing the FIFO by means
of RFOM.
Bit 2 = reserved. Forced to 0 by hardware.
Bits 1:0 = FMP[1:0] FIFO Message Pending
Read
These bits indicate how many messages are pending in the receive FIFO.
FMP is increased each time the hardware stores a new message in to the FIFO. FMP is
decreased each time the software releases the output mailbox by setting the RFOM bit.
CAN Interrupt Enable Register (CIER)
Read/ write
Reset value: 0000 0000 (00h)
All bits of this register are set and cleared by software.
WKUIE
7
0
7
0
0
RFOM
0
Doc ID 12370 Rev 8
FOVR
0
FOVIE0
FULL
FFIE0
0
FMPIE0
FMP1
ST72561-Auto
TMEIE
FMP0
0
0