ST10F269Z2 STMicroelectronics, ST10F269Z2 Datasheet - Page 117

• Manufacturer Part Number: ST10F269Z2
• Description: 16-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST10F269Z2

• Single Voltage Supply: 5V ±10% (EMBEDDED REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).
• Temperature Ranges: -40 +125 °C / -40 to 85 °C

ST10F269
maximum of 1038 TCL (4 TCL + 10 TCL + 1024
TCL). The system configuration is latched from
PORT0 after a duration of 8 TCL / 4 CPU clocks (6
TCL / 3 CPU clocks if PLL is bypassed) and in
case of external fetch, ALE, RD and R/W pins are
driven to their inactive level. Program execution
starts from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timings
of synchronous reset sequence are summarized
in Figure 57. Refer to Table 38 for PORT0 latched
configuration.
Figure 57 : Synchronous Warm Reset Sequence External Fetch (4 TCL < RSTIN pulse < 1038 TCL)
Note
18.3 - Software Reset
The reset sequence can be triggered at any time
using the protected instruction SRST (software
reset).
deliberately within a program, for example to leave
bootstrap loader mode, or upon a hardware trap
that reveals a system failure.
Upon execution of the SRST instruction, the
internal reset sequence (1024 TCL) is started.
The microcontroller behavior is the same as for a
short
P0.12...P0.6 bits are latched at the end of the
1) RSTIN assertion can be released there.
3) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
4) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
5) If during the reset condition (RSTIN low), V
ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low.
CPU
CPU Clock
RSTIN
RPD
RSTOUT
ALE
RD
PORT0
Internal reset signal
hardware
This
= f
XTAL
/ 2), else it is 4 CPU clock cycles (8 TCL).
instruction
1)
reset,
4 TCL 10 TCL
min.
200 A Discharge
min.
can
except
2)
be
that
Internally pulled low
executed
RPD
1024 TCL
voltage drops below the threshold voltage (typically 2.5V for 5V operation), the
only
If V
Reset is not entered.
RPD
Reset Configuration
> 2.5V Asynchronous
3)
Note
reset sequence, while previously latched values of
P0.5...P0.2 are cleared.
18.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during
the initialization or when it is not regularly serviced
during program execution it will overflow and it will
trigger the reset sequence.
Unlike
watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY,
or if READY is sampled active (low) after the
1
2) Maximum internal synchronization is 6 CPU cycles (12
TCL).
6 or 8 TCL
2
- If the RSTIN pin level is sampled low, the
reset sequence is extended until RSTIN
level becomes high leading to a long
hardware
asynchronous
signal duration has lasted longer than
1040TCL.
- If the V
5)
the RPD pin threshold, the reset is
processed as an asynchronous reset.
hardware
3
4
4)
5
5 TCL
for system start-up configuration
Latching point of PORT0
RPD
6
and
reset
7
voltage has dropped below
reset)
8
18 - SYSTEM RESET
9
software
(synchronous
because
1st Instr.
resets,
117/184
RSTIN
the
or