ST10F269Z2 STMicroelectronics, ST10F269Z2 Datasheet - Page 153

• Manufacturer Part Number: ST10F269Z2
• Description: 16-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST10F269Z2

• Single Voltage Supply: 5V ±10% (EMBEDDED REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).
• Temperature Ranges: -40 +125 °C / -40 to 85 °C

ST10F269
Table 46 : Multiplexed Bus Characteristics (PQFP144 devices)
Note: 1. Partially tested, guaranteed by design characterization.
V
= 50pF,
Table 47 : Multiplexed Bus Characteristics (TQFP144 devices)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CC
t
CC
t
CC
t
CC
Symbol
42
43
44
45
46
47
48
49
50
51
52
54
56
5
6
7
8
DD
Symbol
= 5V 10%, V
CC
CC
CC
CC
SR
SR
CC
CC
CC
SR
SR
CC
CC
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD, WR
(with RW-delay)
ALE fall. edge to RdCS, WrCS
(with RW delay)
ALE fall. edge to RdCS, WrCS
(no RW delay)
Address float after RdCS,
WrCS (with RW delay)
Address float after RdCS,
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
SS
Parameter
= 0V, T
Parameter
A
= -40 to +125°C, C
1
1
1
1
5.625 + t
0.625 + t
5.625 + t
5.625 + t
Minimum
Maximum CPU Clock =
15.5 + t
-5.5 + t
28 + t
10 + t
7 + t
6 + t
6 + t
min.
Max. CPU Clock
–
–
–
–
0
–
A
A
A
A
A
F
F
L
C
C
= 40MHz
A
C
32MHz
16.5 + t
ALE cycle time = 6 TCL + 2t
32MHz CPU clock without wait states).
16.5 + t
Maximum
4 + t
max.
12.5
–
–
0
–
–
–
–
–
–
–
–
–
–
C
C
F
2 TCL - 9.5 + t
3 TCL - 9.5 + t
2 TCL - 19 + t
2 TCL - 19 + t
2 TCL - 15+ t
TCL - 5.5+ t
TCL - 10 + t
TCL - 10 + t
TCL - 10 + t
-5.5 + t
TCL - 15+ t
Minimum
min.
1/2 TCL = 1 to 40MHz
Variable CPU Clock
–
–
–
–
0
–
1/2 TCL = 1 to 32MHz
Variable CPU Clock
A
A
C
F
F
C
C
A
A
A
A
A
2 TCL - 21 + t
3 TCL - 21 + t
2 TCL - 8.5+t
+ t
Maximum
C
max.
TCL
+ t
–
–
0
–
–
–
–
–
–
–
–
–
–
F
(187.5ns at
F
C
C
153/184
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns