ST10F269Z2 STMicroelectronics, ST10F269Z2 Datasheet - Page 82

• Manufacturer Part Number: ST10F269Z2
• Description: 16-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST10F269Z2

• Single Voltage Supply: 5V ±10% (EMBEDDED REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).
• Temperature Ranges: -40 +125 °C / -40 to 85 °C

12 - PARALLEL PORTS
Port 5 pins have a special port structure (see Figure 35), first because it is an input only port, and second
because the analog input channels are directly connected to the pins rather than to the input latches.
Figure 35 : Block Diagram of a Port 5 Pin
12.8.2 - Port 5 Schmitt Trigger Analog Inputs
A Schmitt trigger protection can be activated on each pin of Port 5 by setting the dedicated bit of register
P5DIDIS.
P5DIDIS (FFA4h / D2h)
12.9 - Port 6
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the
corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode
via the open drain control register ODP6.
DP6 (FFCEH / E7H)
82/184
DIS.15
P6 (FFCCh / E6h)
P5DIDIS.y
P6.y
P5DI
RW
15
15
15
-
-
DIS.14
P5DI
RW
14
14
14
-
-
DIS.13
P5DI
RW
13
13
13
-
-
Port 5 Digital Disable Register Bit y
P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigger enabled)
P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled,
necessary for input leakage current reduction)
Port Data Register P6 Bit y
DIS.12
P5DI
RW
12
12
12
-
-
DIS.11
P5DI
to Sample + Hold
RW
11
11
11
-
-
Circuit
Read
Buffer
DIS.10
P5DI
RW
10
10
10
-
-
Read Port P5.y
DIS.9
P5DI
RW
9
9
9
-
-
DIS.8
P5DI
RW
Channel
8
8
8
-
-
Select
SFR
SFR
SFR
DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0
DIS.7
P5DI
P6.7
RW
RW
RW
Clock
Latch
Input
7
7
7
DIS.6
P5DI
P6.6
RW
RW
RW
6
6
6
Analog
Switch
DIS.5
P5DI
P6.5
RW
RW
RW
5
5
5
DIS.4
P5DI
P6.4
RW
RW
RW
4
4
4
P5.y/ANy
DIS.3
P5DI
P6.3
RW
RW
RW
3
3
3
Reset Value: 0000h
Reset Value: --00h
Reset Value: --00h
DIS.2
P5DI
P6.2
RW
RW
RW
2
2
2
y = 15...0
ST10F269
DIS.1
P5DI
P6.1
RW
RW
RW
1
1
1
DIS.0
P5DI
P6.0
RW
RW
RW
0
0
0