ST10F269Z2 STMicroelectronics, ST10F269Z2 Datasheet - Page 181

• Manufacturer Part Number: ST10F269Z2
• Description: 16-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST10F269Z2

• Single Voltage Supply: 5V ±10% (EMBEDDED REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).
• Temperature Ranges: -40 +125 °C / -40 to 85 °C

1 - DESCRIPTION
This Errata sheet describes the functional and electrical problems known in the D revision of the
ST10F269Zxxx.
The revision number can be found in the third line on the ST10F269 package. It looks like: ’xxxxxxxxx D’
where "D" identifies the revision number.
2 - FUNCTIONAL PROBLEMS
The following malfunctions are known in this step:
2.1 - PWRDN.1 - Execution of PWRDN Instruction
When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is clear in
SYSCON register) or while at least one of the port 2 pins used to exit from power-down mode (if PWRD-
CFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the
PWRDN instruction is ignored.
However, under the conditions described below, the PWRDN instruction is not ignored, and no further
instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state.
This problem only occurs in the following situations:
a) The instructions following the PWRDN instruction are located in an external memory, and a multi-
b) The instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral
Note: The on-chip peripherals are still working correctly, in particular the Watchdog Timer, if not disabled,
resets the device upon an overflow. Interrupts and PEC transfers, however, cannot be processed. In case
NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered.
No problem occurs if the NMI pin is low (if PWRDCFG = 0) or if all P2 pins used to exit from power-down
mode are at inactive level (if PWRDCFG = 1): the chip normally enters powerdown mode.
Workaround:
Ensure that no instruction that writes to external memory or an XPeripheral preceeds the PWRDN
instruction, otherwise insert a NOP instruction in front of PWRDN. When a multiplexed bus with memory
tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM.
September 2003
plexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is used.
Or
(XRAM,CAN), and the instructions following the PWRDN instruction are located in external memory.
In this case, the problem occurs for any bus configuration.
LIMITATIONS AND CORRECTIONS
ERRATA SHEET
ST10F269Zxxx-D
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