TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 16

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(Operate oscillator and DFM)
(Operate only oscillator)
(Operate only oscillator)
(Operate only oscillator)
(Operate only oscillator)
Note 1: It’s prohibited to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use of DFM.
Note 2: If you shift from NORMAL mode with use of DFM to NORMAL mode, the instruction should be separated into two
Note 3: It’s prohibited to shift from NORMAL mode with use of DFM to STOP mode directly. You should set NORMAL mode
(I/O operate)
IDLE2 mode
IDLE1 mode
clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (the X1, X2, XT1 and XT2 pins
and DFM).
from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> is
called the system clock f
one cycle of f
(I/O operate)
(I/O operate)
(I/O operate)
(I/O operate)
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual
Figure 3.3.1 shows a transition figure.
The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input
（DFM start up/stop/change write to DFMCR0<ACT1:0> register）
procedures as below. Change CPU clock
once, and then shift to STOP mode.(You should stop high frequency oscillator after you stop DFM.)
SYS
Interrupt
Instruction
Interrupt
Instruction
is defined to as one state.
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Figure 3.3.1 System Clock Block Diagram
(Note)
(4 × f OSCH /gear
NORMAL mode
FPH
Using DFM
(a)
(b)
(c)
value/2)
. The system clock f
Single clock mode transition figure
Dual clock mode transition figure
Triple clock mode trasision figure
(f
(f
(f
(Stops all circuits)
OSCH
OSCH
OSCH
→
NORMAL
NORMAL
NORMAL mode
SLOW mode
91C025-14
STOP mode
(f
(f
(f
Stop DFM circuit
OSCH
OSCH
OSCH
Instruction
/Gear value/2)
/Gear value/2)
/Gear value/2)
Reset
Reset
Reset
(fs/2)
(Note)
Instruction
Release reset
Release reset
Release reset
/32)
/32)
mode
/32)
mode
SYS
Interrupt
SLOW mode
is defined as the divided clock of f
Instruction
Interrupt
(fs/2)
Instruction
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
(Stops all circuits)
(Stops all circuits)
(Operate only oscillator)
STOP mode
STOP mode
(I/O operate)
IDLE2 mode
IDLE1 mode
TMP91C025
2007-02-28
FPH
, and