TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 194

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.14 LCD Driver Controller (LCDC)
LCD driver LSI.
driver in itself, and the other circuit handles a shift-register type LCD driver that must serially
transfer the display data to LCD driver for each display picture.
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The TMP91C025 incorporates two types liquid crystal display driving circuit for controlling
One circuit handles a RAM build-in type LCD driver that can store display data in the LCD
This section is constituted as follows.
Shift-register type LCD driver control mode (SR mode)
control register before setting start register.
source memory. After that LCDC transmits data of volume of LCD size to external LCD
driver through data bus.
waveform synchronizes with data transmission.
restart.
RAM built-in type LCD driver control mode (RAM mode)
executed LCDC outputs chip select signal to LCD driver connected to the outside from
control pin. (D1BSCP etc.)
by instruction of CPU.
Special mode
(00E3hex). These bits are used when you want to operate LCDD and MELODY circuit
without low frequency clock (XT1, XT2). After reset these two bits are set to “0” and low
clock is supplied each LCDD and MELODY circuit. If you write these bits to 1, TA3OUT
(Generate by timer 3) is supplied each LCDD and MELODY circuit. In this case, you should
set 32 kHz timer 3 frequency. For detail, look AC specification characteristics.
3.14.1 Feature of LCDC of Each Mode
3.14.2 Block Diagram
3.14.3 Control Registers
3.14.4 Shift-register Type LCD Driver Control Mode (SR type)
3.14.5 RAM Built-in Type LCD Driver Control Mode (RAM Type)
Set the mode of operation, start address of source data save memory and LCD size to
After set start register LCDC outputs bus release request to CPU and read data from
At this time, control signals (D1BSCP etc.) connected LCD driver output specified
After finish data transmission, LCDC cancels the bus release request and CPU will
Data transmission to LCD driver is executed by move instruction of CPU.
After setting mode of operation to control register, when move instruction of CPU is
Therefore control of data transmission numbers corresponding to LCD size is controlled
It is assigned <TA3LCDE> at bit6 and <TA3MLDE> at bit4, of EMCCR0 register
3.14.4.1 Settlement of Frame Frequency Function
3.14.4.2 Timer Out LCDCK
3.14.4.3 Transfer Time by Data Bus Width
3.14.4.4 LCDC Operation in HALT Mode
91C025-193
TMP91C025
2007-02-28