TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 25

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Note: Input frequency limitation and correction for DFM
3.3.4
3.3.5
<ACT1:0>
DFM output: f
Lock up timer
<DLUPFG>
System clock f
Recommend to use Input frequency (High-speed oscillation) for DFM in the following condition.
•
•
Prescaler Clock Controller
divide the clock.
divided by 4. The setting of the SYSCR0<PRCK0:1> register determines which clock signal
is input.
Clock Doubler (DFM)
low-frequency oscillator, even though the internal clock is high frequency .
f
f
For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1) there is a prescaler which can
The φT0 clock input to the prescaler is either the clock f
DFM outputs the f
A reset initializes DFM to stop status, setting to DFMCR0-register is needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lock up time.
The following example shows how DFM is used.
OSCH
OSCH
X: Don't care
DFM
DFMCR0
DFMCR1
LUP:
SYS
= 4 to 9 MHz (Vcc = 3.0 to 3.6 V): Write 0BH to DFMCR1
= 4 to 6.75 MHz (Vcc = 2.7 to 3.6 V): Write 0BH to DFMCR1
EQU
EQU
LD
LD
BIT
JR
LD
Starts DFM operation.
Starts lock up.
DFM
00E8H
00E9H
(DFMCR1), 00001011B
(DFMCR0), 01X0XXXXB
(DFMCR0), 10X0XXXXB
5, (DFMCR0)
NZ, LUP
clock signal, which is four times as fast as f
Counts up by f
91C025-23
01
OSCH
During lock up
Ends of lock up.
;
;
;
;
DFM parameter setting.
Set lock up time to 2
Enables DFM operation and starts lock up.
Changes fc from 4 MHz to 16 MHz.
(Changes f
Detects end of lock up.
FPH
Changes from 4 MHz to 16 MHz.
divided by 4 or the clock fc/16
After lock up
SYS
from 2 MHz to 8 MHz.)
10
12
OSCH
/4 MHz.
. It can use the
TMP91C025
2007-02-28