TMP86xy09NG Toshiba, TMP86xy09NG Datasheet - Page 107

• Manufacturer Part Number: TMP86xy09NG
• Manufacturer: Toshiba

Specifications of TMP86xy09NG

• Package: SDIP32
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 8/16
• Ram Size: 256/512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: √
• Dual Clock: √
• Clock Gear: -
• Number Of I/o Ports: 26
• Power Supply (v): 2.7 to 5.5

Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz)
9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4)
able to enter the 16-bit PPG mode.
the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is
switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is
switched to the opposite state again when a match between the up-counter and the timer register (TTREG3,
TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time.
generated. Upon reset, the timer F/F4 is cleared to 0.
PWREG3 → PWREG4) (Programming only the upper or lower byte should not be attempted.)
mum frequency to be supplied is fc/2
SLEEP1/2 mode.
This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad-
The counter counts up using the internal clock or external clock. When a match between the up-counter and
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
(The logic level output from the
Set the lower byte and upper byte in this order to program the timer register. (TTREG3 → TTREG4,
For PPG output, set the output latch of the I/O port to 1.
Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since
Note 2: When the timer is stopped during PPG output, the
Note 3: i = 3, 4
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maxi-
PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values pro-
grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi.
Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not
be obtained.
stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not change
TC4CR<TFF4> upon stopping of the timer.
Example: Fixing the
CLR (TC4CR).3: Stops the timer
CLR (TC4CR).7: Sets the
LDW
LDW
LD
LD
LD
PPG
Setting ports
(PWREG3), 07D0H
(TTREG3), 8002H
(TC3CR), 33H
(TC4CR), 057H
(TC4CR), 05FH
4 pin to the high level when the TimerCounter is stopped
PPG
PPG
4
4 pin is the opposite to the timer F/F4.)
Hz in the NORMAL1 or IDLE1 mode, and fc/2
4 pin to the high level
Page 97
: Sets the cycle period.
: Sets the operating clock to fc/2
: Sets TFF4 to the initial value 0, and 16-bit
: Sets the pulse width.
: Starts the timer.
(lower byte).
PPG mode (upper byte).
PPG
4 pin holds the output status when the timer is
3
, and16-bit PPG mode
4
to in the SLOW1/2 or
TMP86C809NG