TMP86xy09NG Toshiba, TMP86xy09NG Datasheet - Page 57

• Manufacturer Part Number: TMP86xy09NG
• Manufacturer: Toshiba

Specifications of TMP86xy09NG

• Package: SDIP32
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 8/16
• Ram Size: 256/512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: √
• Dual Clock: √
• Clock Gear: -
• Number Of I/o Ports: 26
• Power Supply (v): 2.7 to 5.5

5. I/O Ports
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-
gram.
port.
The TMP86C809NG have 4 parallel input/output ports as follows.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
Note: The positions of the read and write cycles may vary, depending on the instruction.
Port P0
Port P1
Port P2
Port P3
Data input
Output strobe
Data Output
execution cycle
execution cycle
nput strobe
nstruction
nstruction
Primary Function
8-bit I/O port
7-bit I/O port
3-bit I/O port
8-bit I/O port
Figure 5-1 Input/Output Timing (Example)
S0
S0
External interrupt input, Timer/Counter input/output, serial interface input/output.
External interrupt input and divider output
External interrupt input and STOP mode release signal input
Analog input, STOP mode release signal input and Timer/Counter input/output
Fetch cycle
Fetch cycle
S1
S1
S2
S2
S3
S3
Page 47
S0
S0
(b) Output timing
(a) nput timing
: LD A, (x)
: LD (x), A
Fetch cycle
Fetch cycle
Old
S1
S1
Secondary Functions
S2
S2
S3
S3
S0
S0
Read cycle
Write cycle
S1
S1
S2
S2
New
S3
S3
TMP86C809NG