TMP86xy09NG Toshiba, TMP86xy09NG Datasheet - Page 124

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TMP86xy09NG

Manufacturer Part Number
TMP86xy09NG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy09NG

Package
SDIP32
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
8/16
Ram Size
256/512
Driver Led
8
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
1
I2c/sio Channels
-
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
6
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
1
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Dual Clock
Clock Gear
-
Number Of I/o Ports
26
Power Supply (v)
2.7 to 5.5
11.3 SEI Operation
11.3 SEI Operation
11.3.1 Controlling SEI clock polarity and phase
11.3.2 SEI data and clock timing
neously. The serial clock synchronizes the timing at which information on the two serial data lines are shifted or
sampled. Slave device can be selected individually using the slave select pin (
data on the SEI bus cannot be taken in.
During a SEI transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simulta-
When operating as the master devices, the
using two bits, CPHA and CPOL (SECR<CPHL,CPOL>).
fected).
the same clock phase and polarity.
that of the slave device to which to transfer.
eral devices. Refer to Section “" 11.5 SEI Transfer Formats "”.
The SEI clock allows its phase and polarity to be selected in software from four combinations available by
The clock polarity is set by CPOL to select between active-high or active-low (The transfer format is unaf-
The clock phase is set by CPHA. The master device and the slave devices to communicate with must have
If multiple slave devices with different transfer formats exist on the same bus, the format can be changed to
The programmable data and clock timing of SEI allows connection to almost all synchronous serial periph-
Table 11-2 Clock Phase and Polarity
CPHA
CPOL
SEI control register (SECR 002AH) bit 2
SEI control register (SECR 002AH) bit 3
SS
pin can be used to indicate multiple-master bus connection.
Page 114
SS
pin). For unselected slave devices,
TMP86C809NG

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