TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet
TMP86xy49UG/F/NG
Specifications of TMP86xy49UG/F/NG
Related parts for TMP86xy49UG/F/NG
TMP86xy49UG/F/NG Summary of contents
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Bit Microcontroller TLCS-870/C Series TMP86PM49UG ...
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... Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations ...
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Differences among Products Differences in Functions 86CH49 86CM49 16 Kbytes 32 Kbytes ROM (Mask) (Mask) RAM 512 bytes 1 Kbyte DBR(note1) (Flash control register not contained) I/O High-current port Interrupt Timer/counter UART SIO Key-on wake-up 10-bit AD ...
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OLD name P60(AIN00) P61(AIN01) P62(AIN02) P63(AIN03) P64(AIN04) P65(AIN05) P66(AIN06) AD Converter P67(AIN07) analog input pin name P70(AIN10) P71(AIN11) P72(AIN12) P73(AIN13) P74(AIN14) P75(AIN15) P76(AIN16) P77(AIN17) 0000:AIN00 0001:AIN01 0010:AIN02 0011:AIN03 0100:AIN04 0101:AIN05 0110:AIN06 ADCCR1 register <SAIN> 0111:AIN07 function name 1000:AIN10 1001:AIN11 1010:AIN12 ...
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Differences in Electrical Characteristics 86CH49 86CM49 86CS49 86PM49 [V] [V] 5.5 5.5 4.5 4.5 3.6 3.6 (a) 3.0 3.0 2.7 2.7 2.0 1.8 1 [MHz] 1 4.2 (a) 1.8V to 5.5V (-40 to 85°C) (a) 2.0V ...
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TMP86PM49UG ...
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Date Revision 2006/5/22 1 2007/6/29 2 2008/8/29 3 Revision History First Release Contents Revised Contents Revised ...
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Caution in Setting the UART Noise Rejection Time When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com- bination "O" is available but please do not select the combination "–". The ...
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...
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Table of Contents Differences among Products TMP86PM49UG 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Using data transfer instructions 3.3.3 Interrupt return ........................................................................................................................................ 41 3.4 Software Interrupt (INTSW ...
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TimerCounter 1 (TC1) 8.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NORMAL2 → SLOW2 → SLOW1) 11.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) 12. Asynchronous Serial interface (UART1 ) 12.1 Configuration . . . . . . . . . . . . . ...
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Receive mode 14.3.2.3 Transmit/receive mode 14.3.3 Transfer modes................................................................................................................................... 165 14.3.3.1 Transmit mode 14.3.3.2 Receive mode 14.3.3.3 Transmit/receive mode 15. Synchronous Serial Interface (SIO2) 15.1 Configuration . . . . . . . . . . . . . . ...
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Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). vii ...
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viii ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • ...
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Features 8. 8-bit timer counter : Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 9. 8-bit UART : 2 ch 10. High-Speed SIO: 2ch 11. Serial Bus ...
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Pin Assignment (INT3/TC2) P15 ( /TC5) P16 PDO5/PWM5 ( /TC6) P17 PDO6/PWM6/PPG6 (SCL) P50 (SDA) P51 P52 P53 P54 P30 P31 P32 P33 P34 P35 P36 P37 ...
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Block Diagram 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86PM49UG ...
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Pin Names and Functions The TMP86PM49UG has MCU mode and PROM mode. Table 1-1 shows the pin functions in MCU mode. The PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/3) Pin Name ...
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Pin Names and Functions Table 1-1 Pin Names and Functions(2/3) Pin Name P20 INT5 STOP P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 SCK2 P45 SO2 P44 SI2 P43 P42 TXD2 P41 RXD2 P40 P54 P53 P52 ...
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Table 1-1 Pin Names and Functions(3/3) Pin Name Pin Number P63 23 AIN3 P62 22 AIN2 P61 21 AIN1 P60 20 AIN0 P77 35 AIN15 P76 34 AIN14 P75 33 AIN13 P74 32 AIN12 P73 31 AIN11 P72 30 AIN10 ...
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Pin Names and Functions Page 8 TMP86PM49UG ...
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Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset ...
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System Clock Controller 2.1.3 Data Memory (RAM) The TMP86PM49UG has 1024bytes (Address 0040H to 043FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations ...
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High-frequency clock XIN XOUT XIN (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog ...
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System Clock Controller 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of ...
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Timing Generator Control Register TBTCR (0036H) (DVOEN) (DVOCK) Selection of input to the 7th stage DV7CK of the divider Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” ...
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System Clock Controller (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> ...
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Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. ...
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System Clock Controller IDLE1 mode (a) Single-clock mode IDLE2 mode SLEEP2 mode SLEEP1 mode (b) Dual-clock mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called ...
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System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN STOP STOP mode start Release method for STOP RELM mode Operating mode after STOP RETM mode OUTEN Port output during STOP mode Warm-up time at releasing WUT ...
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System Clock Controller 2.2.4 Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the (STOP3 to STOP0) which is controlled by the STOP mode release control register (STOPCR). The pin is also ...
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Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 JRS F, SINT5 LD (SYSCR1), 01010000B DI SET (SYSCR1). 7 SINT5: RETI STOP pin XOUT pin NORMAL operation Confirm by program that the STOP ...
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System Clock Controller STOP mode is released by the following sequence the dual-clock mode, when returning to NORMAL2, both the high-frequency and low warm-up period is inserted to allow oscillation time to stabilize. During warm ...
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Figure 2-9 STOP Mode Start/Release Page 21 TMP86PM49UG ...
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System Clock Controller 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and ...
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Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 ...
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System Clock Controller Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24 TMP86PM49UG ...
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IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing ...
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System Clock Controller • Start the IDLE0 and SLEEP0 modes • Release the IDLE0 and SLEEP0 modes of TBT and TBTCR<TBTEN>. cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before ...
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Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27 TMP86PM49UG ...
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System Clock Controller 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, ...
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Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC6,TC5), clear SYSCR2<SYSCK> to switch the main system clock to the ...
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System Clock Controller Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30 TMP86PM49UG ...
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Reset Circuit The TMP86PM49UG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and ...
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Reset Circuit 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or ...
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Reset Circuit Page 34 TMP86PM49UG ...
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Interrupt Control Circuit The TMP86PM49UG has a total of 24 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt ...
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Interrupt enable register (EIR) The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by ...
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Individual interrupt enable flags (EF23 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting ...
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Interrupt enable register (EIR) Interrupt Latches 15 14 ILH,ILL (003DH, 003CH) IL15 IL14 ILE (002EH) IL23 to IL2 Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note ...
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Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after ...
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Interrupt Sequence A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF ...
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Example :Save/store register using data transfer instructions PINTxx: LD (interrupt processing) LD RETI Main task Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as ...
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Software Interrupt (INTSW) Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter- rupt ...
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External Interrupts The TMP86PM49UG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. ...
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External Interrupts External Interrupt Control Register EINTCR 7 (0037H) INT1NC INT0EN INT1NC INT0EN INT3 ES INT2 ES INT1 ES Note 1: fc: High-frequency clock [Hz], *: Don’t care Note 2: When the system clock frequency is switched between high ...
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Special Function Register (SFR) The TMP86PM49UG adopts the memory mapped I/O system, and all peripheral control and data transfers are per- formed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on ...
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SFR Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Note 1: Do not access reserved areas by the program. Note ...
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DBR Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH 0F8DH 0F8EH 0F8FH 0F90H 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH Address 0FA0H : : 0FBFH ...
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DBR Note 2: − ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 48 ...
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I/O Ports The TMP86PM49UG has 8 parallel input/output ports (56 pins) as follows. Primary Function Port P0 8-bit I/O port Port P1 8-bit I/O port Port P2 3-bit I/O port Port P3 8-bit I/O port Port P4 8-bit I/O ...
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Port P0 (P07 to P00) 5.1 Port P0 (P07 to P00) Port 8-bit input/output port. Port P0 is also used as an external interrupt input, a serial interface input/output and an UART input/output. When used as ...
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P0DR P07 P06 P05 P04 (0000H) INT2 SO1 SCK1 R/W P0OUTCR (0008H) P0OUTCR Port P0 output circuit control (Set for each bit individually) P0PRD P07 P06 P05 P04 (000BH) Read only P03 ...
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Port P1 (P17 to P10) 5.2 Port P1 (P17 to P10) Port 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P1 is also used as a timer/counter input/output, ...
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P17 P16 P15 P14 P1DR TC6 TC5 TC2 TC4 (0001H) INT3 PWM6 PWM5 PWM4 R/W PDO6 PDO5 PDO4 PPG6 PPG4 P1CR (0009H) P1CR I/O control for port P1 (Specified for each bit) ...
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Port P2 (P22 to P20) 5.3 Port P2 (P22 to P20) Port 3-bit input/output port also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con- nection pins. ...
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Port P3 (P37 to P30) (Large Current Port) Port 8-bit input/output port. When used as an input port, the corresponding output latch (P3DR) should be set to "1". During reset, the P3DR is initialized to "1". ...
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Port P4 (P47 to P40) 5.5 Port P4 (P47 to P40) Port 8-bit input/output port. Port P4 is also used as a serial interface input/output and an UART input/output. When used as an input port, a ...
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P4DR (0004H) P47 P46 P45 P44 R/W SO2 SCK2 P4OUTCR (000AH) P4OUTCR Port P4 output circuit control (Set for each bit individually) P4PRD P47 P46 P45 P44 (000EH) Read only P43 P42 ...
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Port P5 (P54 to P50) (Large Current Port) 5.6 Port P5 (P54 to P50) (Large Current Port) Port 5-bit input/output port. Port P5 is also used When used as an input port and ...
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Port P6 (P67 to P60) Port 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P6 is also used as an analog input and key-on wakeup input. Input/output mode ...
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Port P6 (P67 to P60) P6CR2i input P6CR1i input Control input Data input (P6DRi) Data output (P6DRi) OUTTEN Analog input Key-on wakeup STOPkEN P6CR2j input P6CR1j input Data input (P6DRj) Data output (P6DRj) OUTTEN Analog input Note 1: i ...
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P6DR P67 P66 P65 P64 (0006H) AIN7 AIN6 AIN5 AIN4 R/W STOP3 STOP2 STOP1 STOP0 P6CR1 (0F9BH) P6CR1 I/O control for port P6 (Specified for each bit P6CR2 (0F9CH) P6CR2 P6 ...
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Port P7 (P77 to P70) 5.8 Port P7 (P77 to P70) Port 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P7 is also used as an analog input. ...
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P7CR2i P7CR2i input P7CR1i P7CR1i input Control input Data input (P7DRi) Data output (P7DRi) STOP OUTTEN Analog input AINDS SAIN Note Note 2: STOP is bit7 in SYSCR1. Note 3: SAIN is AD input ...
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Port P7 (P77 to P70) Page 64 TMP86PM49UG ...
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Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The ...
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Watchdog Timer Control 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog ...
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Watchdog Timer Control Register WDTCR1 (0034H) (ATAS) WDTEN Watchdog timer enable/disable Watchdog timer detection time WDTT [s] WDTOUT Watchdog timer output select Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”. ...
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Watchdog Timer Control 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master ...
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Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is maximum ...
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Address Trap 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register WDTCR1 (0034H) Select address trap generation in ATAS ...
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Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the ...
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Address Trap Page 72 TMP86PM49UG ...
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Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration MPX 23 15 fc/2 or fs/2 21 ...
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Time Base Timer Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling ...
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Divider Output ( DVO Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from 7.2.1 Configuration Output latch D Q Data output MPX ...
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Divider Output (DVO) Example :1.95 kHz pulse output (fc = 16.0 MHz) Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz 32.768 kHz ) DVOCK LD (TBTCR) , 00000000B LD (TBTCR) , 10000000B Divider ...
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TimerCounter 1 (TC1) 8.1 Configuration Figure 8-1 TimerCounter 1 (TC1) Page 77 TMP86PM49UG ...
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TimerCounter Control 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 14 TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) TimerCounter 1 Control Register ...
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Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other ...
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Function 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the ...
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Timer start Source clock Counter 0 1 TC1DRA ? INTTC1 interruput request Source clock m − − 1 Counter m − 1 TC1DRB ? ACAP1 Figure 8-2 Timer Mode Timing Chart n − ...
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Function 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge ...
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Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Figure 8-3 External Trigger Timer Mode Timing Chart ...
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Function 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the ...
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Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the ...
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Function 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or ...
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Example :Duty measurement (resolution fc/2 CLR LD DI SET PINTTC1: CPL JRS RETI SINTTC1 RETI : VINTTC1: DW TC1 pin INTTC1 interrupt request INTTC1SW 7 [Hz]) (INTTC1SW INTTC1 ...
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Function Count start TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request Count start TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request Trigger (a) Single-edge capture 0 1 ...
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Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input ...
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Function Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs ( MHz) LD LDW LDW LD Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc ...
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Timer start Internal clock Counter TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Count start TC1 pin input Trigger Internal clock Counter TC1DRB m TC1DRA PPG pin output ...
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Function Page 92 TMP86PM49UG ...
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Timer/Counter2 (TC2) 9.1 Configuration Port H (Note) TC2 pin Window 23, 15 fc/2 fs/2 A 13, 5 fc/2 fs/2 B Timer/ 8 fc/2 C event counter 3 fc TC2S TC2CK TC2CR ...
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Control 9.2 Control The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR TC2DR (0025H, 0024H) (Initial value: 1111 1111 1111 1111 TC2CR (0023H) TC2S TC2 ...
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Function The timer/counter 2 has three operating modes: timer, event counter and window modes. And selected as the source clock in timer mode, when switching the timer mode from SLOW1 to NORMAL2, the timer/counter2 ...
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Function Source clock Up-counter TC2DR INTTC2 interrupt Timer start Figure 9-2 Timer Mode Timing Chart Page 96 TMP86PM49UG Match detect Counter clear ...
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Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are com- pared with the contents of the up counter match is found, an INTTC2 ...
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Function Example :Generates an interrupt, inputting “H” level pulse width of 120 ms or more. ( MHz, TBTCR<DV7CK> = “0” ) TC2 pin input Internal clock Counter TC2DR INTTC2 interrupt LDW (TC2DR), 00EAH ; Sets TC2DR ...
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TimerCounter (TC3, TC4) 10.1 Configuration 11 3 fc fc/2 16-bit mode G fc TC4 pin H S TC4M ...
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Configuration 10.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 7 6 (0014H) R/W PWREG3 7 6 (0018H) R/W Note 1: ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 10- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the ...
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Configuration The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 7 6 (0015H) R/W PWREG4 7 6 (0019H) R/W Note 1: Do not ...
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Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending ...
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Configuration Table 10-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- ...
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Configuration TC4CR<TC4S> Internal Source Clock Counter TTREG4 ? INTTC4 interrupt request Figure 10-2 8-Bit Timer Mode Timing Chart (TC4) 10.3.2 8-Bit Event Counter Mode (TC3 the 8-bit event counter mode, the up-counter counts up at the falling ...
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Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift ...
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Configuration Figure 10-4 8-Bit PDO Mode Timing Chart (TC4) Page 108 TMP86PM49UG ...
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Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up-counter counts up using the internal clock. When a match between ...
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Configuration Figure 10-5 8-Bit PWM Mode Timing Chart (TC4) Page 110 TMP86PM49UG ...
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Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the ...
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Configuration 10.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. ...
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CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, ...
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Configuration Figure 10-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 114 TMP86PM49UG ...
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Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The ...
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Configuration Figure 10-8 16-Bit PPG Mode Timing Chart (TC3 and TC4) Page 116 TMP86PM49UG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit ...
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Configuration 10.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, ...
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TimerCounter (TC5, TC6) 11.1 Configuration 11 3 fc fc/2 16-bit mode G fc TC6 pin H S TC6M ...
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Configuration 11.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 7 6 (0016H) R/W PWREG5 7 6 (001AH) R/W Note 1: ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 11- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the ...
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Configuration The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 7 6 (0017H) R/W PWREG6 7 6 (001BH) R/W Note 1: Do not ...
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Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR<TC5CK>. Set the timer start control and timer F/F control by programming TC6S and TFF6, respectively. Note 7: The operating clock settings are limited depending ...
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Configuration Table 11-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16- ...
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Configuration TC6CR<TC6S> Internal Source Clock Counter TTREG6 ? INTTC6 interrupt request 11.3.2 8-Bit Event Counter Mode (TC5 the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj ...
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Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift ...
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Configuration Figure 11-4 8-Bit PDO Mode Timing Chart (TC6) Page 128 TMP86PM49UG ...
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Pulse Width Modulation (PWM) Output Mode (TC5, 6) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up-counter counts up using the internal clock. When a match between ...
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Configuration Figure 11-5 8-Bit PWM Mode Timing Chart (TC6) Page 130 TMP86PM49UG ...
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Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascad- able to form a 16-bit timer. When a match between the up-counter and the ...
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Configuration 11.3.6 16-Bit Event Counter Mode (TC5 and 6) In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5 and 6 are cascadable to form a 16-bit event counter. ...
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CLR (TC6CR).3: Stops the timer. CLR (TC6CR).7 : Sets the Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, ...
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Configuration Figure 11-7 16-Bit PWM Mode Timing Chart (TC5 and TC6) Page 134 TMP86PM49UG ...
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Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascad- able to enter the 16-bit PPG mode. The ...
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Configuration Figure 11-8 16-Bit PPG Mode Timing Chart (TC5 and TC6) Page 136 TMP86PM49UG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a 16-bit ...
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Configuration 11.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, ...
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Asynchronous Serial interface (UART1 ) 12.1 Configuration UART control register 1 UART1CR1 3 2 INTTXD1 INTRXD1 S fc/ fc/26 C fc/52 fc/104 fc/208 fc/416 F INTTC3 G H fc/96 Baud rate generator Figure 12-1 ...
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Control 12.2 Control UART1 is controlled by the UART1 Control Registers (UART1CR1, UART1CR2). The operating status can be monitored using the UART status register (UART1SR). UART1 Control Register1 7 6 UART1CR1 (0F95H) TXE RXE TXE Transfer operation RXE Receive ...
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UART1 Status Register UART1SR (0F95H) PERR FERR OERR RBFL PERR Parity error flag FERR Framing error flag OERR Overrun error flag RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty ...
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Transfer Data Format 12.3 Transfer Data Format In UART1, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART1CR1<STBT>), and parity (Select parity in UART1CR1<PE>; even- or odd-numbered parity by UART1CR1<EVEN>) are added ...
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Transfer Rate The baud rate of UART1 is set of UART1CR1<BRG>. The example of the baud rate are shown as follows. Table 12-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC3 is used as the ...
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STOP Bit Length 12.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART1CR1<STBT>. 12.7 Parity Set parity / no parity by UART1CR1<PE> and set parity type (Odd- or Even-numbered) by UART1CR1<EVEN>. 12.8 ...
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Status Flag 12.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the RD1BUF is read ...
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Status Flag UART1SR<RBFL> RXD1 pin Shift register RD1BUF UART1SR<OERR> INTRXD1 interrupt Note:Receive operations are disabled until the overrun error flag UART1SR<OERR> is cleared. 12.9.4 Receive Data Buffer Full Loading the received data in RD1BUF sets receive data buffer full ...
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TD1BUF xxxx ***** 1 1xxxx0 Shift register TXD1 pin Start UART1SR<TBEP> INTTXD1 interrupt Figure 12-9 Generation of Transmit Data Buffer Empty 12.9.6 Transmit End Flag When data are transmitted and no data is in TD1BUF (UART1SR<TBEP> = “1”), transmit end ...
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Status Flag Page 148 TMP86PM49UG ...
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Asynchronous Serial interface (UART2 ) 13.1 Configuration UART control register 1 UART2CR1 3 2 INTTXD2 INTRXD2 S fc/ fc/26 C fc/52 fc/104 fc/208 fc/416 F INTTC5 G H fc/96 Baud rate generator Figure 13-1 ...
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Control 13.2 Control UART2 is controlled by the UART2 Control Registers (UART2CR1, UART2CR2). The operating status can be monitored using the UART status register (UART2SR). UART2 Control Register1 7 6 UART2CR1 (0F98H) TXE RXE TXE Transfer operation RXE Receive ...
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UART2 Status Register UART2SR (0F98H) PERR FERR OERR RBFL PERR Parity error flag FERR Framing error flag OERR Overrun error flag RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty ...
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Transfer Data Format 13.3 Transfer Data Format In UART2, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART2CR1<STBT>), and parity (Select parity in UART2CR1<PE>; even- or odd-numbered parity by UART2CR1<EVEN>) are added ...
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Transfer Rate The baud rate of UART2 is set of UART2CR1<BRG>. The example of the baud rate are shown as follows. Table 13-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC5 is used as the ...
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STOP Bit Length 13.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART2CR1<STBT>. 13.7 Parity Set parity / no parity by UART2CR1<PE> and set parity type (Odd- or Even-numbered) by UART2CR1<EVEN>. 13.8 ...
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Status Flag 13.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART2SR<PERR> is set to “1”. The UART2SR<PERR> is cleared to “0” when the RD2BUF is read ...
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Status Flag UART2SR<RBFL> RXD2 pin Shift register RD2BUF UART2SR<OERR> INTRXD2 interrupt Note:Receive operations are disabled until the overrun error flag UART2SR<OERR> is cleared. 13.9.4 Receive Data Buffer Full Loading the received data in RD2BUF sets receive data buffer full ...
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TD2BUF xxxx ***** 1 1xxxx0 Shift register TXD2 pin Start UART2SR<TBEP> INTTXD2 interrupt Figure 13-9 Generation of Transmit Data Buffer Empty 13.9.6 Transmit End Flag When data are transmitted and no data is in TD2BUF (UART2SR<TBEP> = “1”), transmit end ...
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Status Flag Page 158 TMP86PM49UG ...
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Synchronous Serial Interface (SIO1) The serial interfaces connect to an external device via SI1, SO1, and When these pins are used as serial interface, the output latches for each port should be set to "1". 14.1 Configuration Internal data ...
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Control 14.2 Control The SIO is controlled using the serial interface control register (SIO1CR). The operating status of the serial inter- face can be inspected by reading the status register (SIO1CR). Serial Interface Control Register SIO1CR 7 6 (0020H) ...
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Serial Interface Status Register SIO1SR (0021H) SIOF SEF TXF Serial transfer operation status SIOF monitor SEF Number of clocks monitor TXF Transmit buffer empty flag RXF Receive buffer full flag TXERR Transfer operation error flag RXERR Receive ...
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Function 14.3 Function 14.3.1 Serial clock 14.3.1.1 Clock source The serial clock can be selected by using SIO1CR<SCK>. When the serial clock is changed, the writing instruction to SIO1CR<SCK> should be executed while the transfer is stopped (when SIO1SR<SIOF> ...
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External clock When an external clock is selected by setting SIO1CR<SCK> to “111B”, the clock via the pin from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be ...
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Function 14.3.2 Transfer bit direction Transfer data direction can be selected by using SIO1CR<SIODIR>. The transfer data direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIO1CR<SIODIR> should ...
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LSB receive mode LSB receive mode is selected by setting SIO1CR<SIODIR> to “1”, in which case the data is received sequentially beginning with the least significant bit (Bit0). 14.3.2.3 Transmit/receive mode (1) MSB transmit/receive mode MSB transmit/receive mode are ...
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Function (2) During the transmit operation When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0”. In internal clock operation, in case a next transmit data is not written to SIO1TDB, the serial clock stops to “H” level ...
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SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin SCK1 SO1 pin SIO1SR<TXF> INTSIO1 interrupt request SIO1TDB <SIOS> ...
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Function SIO1CR<SIOS> SIO1SR<SIOF> SIO1SR<SEF> pin SCK1 SO1 pin SIO1SR<TXF> SIO1SR<TXERR> INTSIO1 interrupt request SIO1TDB A Writing transmit SIO1CR data A <SIOINH> Figure 14-9 Example of Transmit Error Processingme 14.3.3.2 Receive mode The receive mode is selected by writing “01B” ...
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If received data is not read out from SIO1RDB receive error occurs immediately after shift opera- tion is finished. Then INTSIO1 interrupt request is generated after SIO1SR<RXERR> is set to “1”. (3) Stopping the receive operation There are two ways ...
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Function SIO1CR<SIOS> SIO1SR<SIOF> SIO1SR<SEF> pin SCK1 SI1 pin SIO1SR<RXF> INTSIO1 interrupt request SIO1RDB Figure 14-11 Example of External Clock and MSB Receive Mode (4) Receive error processing Receive errors occur on the following situation. To protect SIO1RDB and the ...
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SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin SCK1 SI1 pin SIO1SR<RXF> SIO1SR<RXERR> INTSIO1 interrupt request SIO1RDB ...
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Function (2) During the transmit/receive operation When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0” and when a data is read from SIO1RDB, SIO1SR<RXF> is cleared to “0”. In internal clock operation, in case of the condition ...
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SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin output SCK1 SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR<TXF> SIO1TDB A Writing transmit data A SIO1SR<RXF> SIO1RDB Figure ...
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Function SIO1CR<SIOS> SIO1SR<SIOF> SIO1SR<SEF> pin output SCK1 SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR<TXF> SIO1TDB A Writing transmit data A SIO1SR<RXF> SIO1RDB Figure 14-14 Example of External Clock and MSB Transmit/Receive Mode (4) Transmit/receive error processing Transmit/receive errors ...
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SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin output SCK1 SO1 pin SI1 pin ...
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Function SIO1CR<SIOS> SIO1SR<SIOF> SIO1SR<SEF> pin output SCK1 SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR<TXF> SIO1TDB A Writing transmit data A SIO1SR<RXF> SIO1SR<RXERR> SIO1RDB SIO1CR<SIOINH> Figure 14-16 Example of Transmit/Receive (Receive) Error Processing pin SCK1 SIO1SR<SIOF> SO1 pin Figure ...
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Synchronous Serial Interface (SIO2) The serial interfaces connect to an external device via SI2, SO2, and When these pins are used as serial interface, the output latches for each port should be set to "1". 15.1 Configuration Internal data ...
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Control 15.2 Control The SIO is controlled using the serial interface control register (SIO2CR). The operating status of the serial inter- face can be inspected by reading the status register (SIO2CR). Serial Interface Control Register 7 6 SIO2CR (0031H) ...
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Serial Interface Status Register SIO2SR (0032H) SIOF SEF TXF Serial transfer operation status SIOF monitor SEF Number of clocks monitor TXF Transmit buffer empty flag RXF Receive buffer full flag TXERR Transfer operation error flag RXERR Receive ...
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Function 15.3 Function 15.3.1 Serial clock 15.3.1.1 Clock source The serial clock can be selected by using SIO2CR<SCK>. When the serial clock is changed, the writing instruction to SIO2CR<SCK> should be executed while the transfer is stopped (when SIO2SR<SIOF> ...
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External clock When an external clock is selected by setting SIO2CR<SCK> to “111B”, the clock via the pin from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be ...
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Function 15.3.2 Transfer bit direction Transfer data direction can be selected by using SIO2CR<SIODIR>. The transfer data direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIO2CR<SIODIR> should ...
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LSB receive mode LSB receive mode is selected by setting SIO2CR<SIODIR> to “1”, in which case the data is received sequentially beginning with the least significant bit (Bit0). 15.3.2.3 Transmit/receive mode (1) MSB transmit/receive mode MSB transmit/receive mode are ...