TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 19

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TMP86xy49UG/F/NG

Manufacturer Part Number
TMP86xy49UG/F/NG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy49UG/F/NG

Package
LQFP64/QFP64/SDIP64
Rom Types (m=mask,p=otp,f=flash)
M/P/F
Rom Size
16/32/60
Ram Size
512/1K/2K
Driver Led
13
Driver Lcd
-
Spi/sio Channels
2
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
56
Power Supply (v)
4.5 to 5.5
1.1 Features
8. 8-bit timer counter : 4 ch
9. 8-bit UART : 2 ch
10. High-Speed SIO: 2ch
11. Serial Bus Interface(I
12. 10-bit successive approximation type AD converter
13. Key-on wakeup : 4 ch
14. Clock operation
15. Low power consumption operation
16. Wide operation voltage:
stop.)
oscillate.)
quency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
puts(CPU restarts).
ruputs. (CPU restarts).
quency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
put.(CPU restarts).
interruput.
- Timer, Event counter, Programmable divider output (PDO),
- Analog input: 16 ch
Single clock mode
Dual clock mode
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre-
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru-
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter-
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre-
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru-
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock.
4.5 V to 5.5 V at 16MHz /32.768 kHz
2.7 V to 5.5 V at 8 MHz /32.768 kHz
1.8 V to 5.5 V at 4.2MHz /32.768 kHz
Pulse width modulation (PWM) output,
Programmable pulse generation (PPG) modes
2
C Bus): 1ch
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