TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 30

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

Timing Generator Control Register
Main system clock
2.2.3 Operation Mode Control Circuit
(0036H)
TBTCR
2.2.2.2
2.2.3.1
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
frequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.
State
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-
(DVOEN)
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
DV7CK
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
7
Machine cycle
Single-clock mode
(1)
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
The TMP86PM49UG is placed in this mode after reset.
1/fc or 1/fs [s]
NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
Selection of input to the 7th stage
of the divider
6
(DVOCK)
S0
5
S1
Machine cycle
DV7CK
Figure 2-5 Machine Cycle
4
(TBTEN)
S2
3
0: fc/2
1: fs
Page 13
8
[Hz]
S3
2
(TBTCK)
1
S0
0
S1
(Initial value: 0000 0000)
S2
TMP86PM49UG
S3
R/W