TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 99

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

8.3 Function
8.3.2 External Trigger Timer Mode
Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin
Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC1 pin
pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising
or falling edge is defined in TC1CR<TC1S>.
of 12/fc [s] or more is required to ensure edge detection. The rejection circuit is turned off in the SLOW1/2 or
SLEEP1/2 mode, but a pulse width of one machine cycle or more is required.
In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1
Since the TC1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width
• When TC1CR<METT1> is set to “1” (trigger start and stop)
• When TC1CR<METT1> is set to “0” (trigger start)
up-counter is cleared and halted and an INTTC1 interrupt request is generated.
and the TC1DRA, the up-counter is cleared and halted without generating an interrupt request.
Therefore, this mode can be used to detect exceeding the specified pulse by interrupt.
up-counter is cleared and halted and an INTTC1 interrupt request is generated.
ing is ignored if detecting it before detecting a match between the up-counter and the TC1DRA.
(fc =16 MHz)
(fc =16 MHz)
When a match between the up-counter and the TC1DRA value is detected after the timer starts, the
If the edge opposite to trigger edge is detected before detecting a match between the up-counter
After being halted, the up-counter restarts counting when the trigger edge is detected.
When a match between the up-counter and the TC1DRA value is detected after the timer starts, the
The edge opposite to the trigger edge has no effect in count up. The trigger edge for the next count-
LDW
DI
SET
EI
LD
LD
LDW
DI
SET
EI
LD
LD
(TC1DRA), 007DH
(EIRL). 5
(TC1CR), 00000100B
(TC1CR), 00100100B
(TC1DRA), 01F4H
(EIRL). 5
(TC1CR), 00000100B
(TC1CR), 01110100B
Page 82
; 1ms ÷ 2
; IMF= “0”
; Enables INTTC1 interrupt
; IMF= “1”
; Selects the source clock and mode
; Starts TC1 external trigger, METT1 = 0
; 4 ms ÷ 2
; IMF= “0”
; Enables INTTC1 interrupt
; IMF= “1”
; Selects the source clock and mode
; Starts TC1 external trigger, METT1 = 1
7
7
/fc = 7DH
/fc = 1F4H
TMP86PM49UG