FAN7930C Fairchild Semiconductor, FAN7930C Datasheet - Page 11

• Manufacturer Part Number: FAN7930C
• Description: The FAN7930C is an active power factor correction (PFC) controller for boost PFC applications that operate in critical conduction mode (CRM)
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN7930C • Rev. 1.0.1
Applications Information
1. Startup: Normally, supply voltage (V
block is fed from the additional power supply, which can
be called standby power. Without this standby power,
auxiliary winding for zero current detection can be used
as a supply source. Once the supply voltage of the PFC
block exceeds 12V, internal operation is enabled until
the voltage drops to 8.5V. If V
current is sinking from V
2. INV Block: Scaled-down voltage from the output is
the input for the INV pin. Many functions are embedded
based on the INV pin: transconductance amplifier,
output OVP comparator, disable comparator, and output
UVLO comparator.
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage-
controlled current source) aids the implementation of the
OVP and disable functions. The output current of the
amplifier changes according to the voltage difference of
the inverting and non-inverting input of the amplifier. To
cancel down the line input voltage effect on power factor
correction, the effective control response of the PFC
block should be slower than the line frequency and this
conflicts with the transient response of controller. Two-
pole one-zero type compensation may be used to meet
both requirements.
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675V
and there is 0.175V hysteresis. The disable comparator
disables operation when the voltage of the inverting
input is lower than 0.35V and there is 100mV hysteresis.
An external small-signal MOSFET can be used to
disable the IC, as shown in Figure 23. The IC operating
current decreases to reduce power consumption if the
IC is disabled. Figure 24 is the timing chart of the
internal circuit near the INV pin when rated PFC output
voltage is 390V
Figure 22.
DC
and V
CC
CC
.
supply voltage is 15V.
Startup Circuit
CC
exceeds V
CC
) of a PFC
Z
, 20mA
11
3. RDY Output: When the INV voltage is higher than
2.24V, RDY output is triggered HIGH and lasts until the
INV voltage is lower than 2.051V. When input AC
voltage is quite high, for example 240V
voltage is always higher than RDY threshold, regardless
of boost converter operation. In this case, the INV
voltage is already higher than 2.24V before PFC V
touches V
HIGH until V
operation stops, RDY is not pulled LOW because the
INV voltage is higher than the RDY threshold. When V
of the PFC drops below 5V, RDY is pulled LOW even
though PFC output voltage is higher than threshold. The
RDY pin output is open drain, so needs an external pull-
up resistor to supply the proper power source. The RDY
pin output remains floating until V
Figure 24.
Figure 23.
START
CC
; however, RDY output is not triggered to
touches V
Timing Chart for INV Block
Circuit Around INV Pin
START
. After boost converter
CC
is higher than 2V.
AC
, PFC output
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CC
CC