FAN9612 Fairchild Semiconductor, FAN9612 Datasheet - Page 4
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FAN9612
Manufacturer Part Number
FAN9612
Description
Manufacturer
Fairchild Semiconductor
Datasheet
1.FAN9612.pdf
(36 pages)
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© 2008 Fairchild Semiconductor Corporation
FAN9611 / FAN9612 • Rev. 1.1.4
Pin Configuration
Pin Definitions
Pin #
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Name
COMP
AGND
PGND
DRV2
DRV1
ZCD1
ZCD2
MOT
OVP
VDD
CS2
CS1
5VB
VIN
SS
FB
Zero Current Detector for Phase 1 of the interleaved boost power stage.
Zero Current Detector for Phase 2 of the interleaved boost power stage.
5V Bias. Bypass pin for the internal supply, which powers all control circuitry on the IC.
Maximum On-Time adjust for the individual power stages.
Analog Ground. Reference potential for all setup signals.
Soft-Start Capacitor. Connected to the non-inverting input of the error amplifier.
Compensation Network connection to the output of the g
Feedback pin to sense the converter’s output voltage; inverting input of the error amplifier.
Output Voltage monitor for the independent, second-level, latched OVP protection.
Input Voltage monitor for brownout protection and input-voltage feedforward.
Power Ground connection.
Gate Drive Output for Phase 2 of the interleaved boost power stage.
Gate Drive Output for Phase 1 of the interleaved boost power stage.
External Bias Supply for the IC.
Current Sense Input for Phase 2 of the interleaved boost power stage.
Current Sense Input for Phase 1 of the interleaved boost power stage.
Figure 5. Pin Layout (Top-View)
4
Description
M
error amplifier
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