FAN4803 Fairchild Semiconductor, FAN4803 Datasheet - Page 4

• Manufacturer Part Number: FAN4803
• Description: To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency at light-load conditions
• Manufacturer: Fairchild Semiconductor

FAN4803
Functional Description
The FAN4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a syn-
chronized Pulse Width Modulation (PWM) controller. It is
distinguished from earlier combo controllers by its low pin
count, innovative input current shaping technique, and very
low start-up and operating currents. The PWM section is
dedicated to peak current mode operation. It uses conven-
tional trailing-edge modulation, while the PFC uses leading-
edge modulation. This patented Leading Edge/Trailing Edge
(LETE) modulation technique helps to minimize ripple cur-
rent in the PFC DC buss capacitor.
The FAN4803 is offered in two versions. The FAN4803-1
operates both PFC and PWM sections at 67kHz, while the
FAN4803-2 operates the PWM section at twice the fre-
quency (134kHz) of the PFC. This allows the use of smaller
PWM magnetics and output filter components, while mini-
mizing switching losses in the PFC stage.
In addition to power factor correction, several protection fea-
tures have been built into the FAN4803. These include soft
start, redundant PFC over-voltage protection, peak current
limiting, duty cycle limit, and under voltage lockout
(UVLO). See Figure 12 for a typical application.
Detailed Pin Descriptions
V
This pin provides the feedback path which forces the PFC
output to regulate at the programmed value. It connects to
programming resistors tied to the PFC output voltage and is
shunted by the feedback compensation network.
I
This pin ties to a resistor or current sense transformer which
senses the PFC input current. This signal should be negative
with respect to the IC ground. It internally feeds the pulse-
by-pulse current limit comparator and the current sense feed-
back signal. The I
back is internally multiplied by a gain of four and compared
against the internal programmed ramp to set the PFC duty
cycle. The intersection of the boost inductor current
downslope with the internal programming ramp determines
the boost off-time.
V
This pin is typically tied to the feedback opto-collector. It is
tied to the internal 5V reference through a 26k resistor and
to GND through a 40k resistor.
I
This pin is tied to the primary side PWM current sense resis-
tor or transformer. It provides the internal pulse-by-pulse
current limit for the PWM stage (which occurs at 1.5V) and
the peak current mode feedback path for the current mode
4
SENSE
LIMIT
EAO
DC
LIMIT
trip level is –1V. The I
SENSE
feed-
control of the PWM stage. The current ramp is offset inter-
nally by 1.2V and then compared against the opto feedback
voltage to set the PWM duty cycle.
PFC OUT and PWM OUT
PFC OUT and PWM OUT are the high-current power driv-
ers capable of directly driving the gate of a power MOSFET
with peak currents up to ±1A. Both outputs are actively held
low when V
V
V
up current is 150µA . The no-load I
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the operating
frequency and the MOSFET gate charge (Qg), average
PFC and PWM output currents can be calculated as I
Qg x F. The average magnetizing current required for any
gate drive transformers must also be included. The V
is also assumed to be proportional to the PFC output voltage.
Internally it is tied to the V
providing redundant high-speed over-voltage protection
(OVP) of the PFC stage. V
UVLO circuitry, enabling the IC at 12V and disabling it at
9.1V. V
bypass capacitor placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
FAN4803.
V
boost inductor or PFC Choke, providing a voltage that is pro-
portional to the PFC output voltage. Since the V
voltage is 16.2V, an internal shunt limits V
an acceptable value. An external clamp, such as shown in
Figure 1, is desirable but not necessary.
V
mum. This limits the maximum V
the IC while allowing a V
V
External series resistance is required in order to limit the
current through this Zener in the case where the V
exceeds the zener clamp level.
CC
CC
CC
CC
CC
OVP. The max current through this zener is 10mA.
is the power input connection to the IC. The V
is typically produced by an additional winding off the
is internally clamped to 16.7V minimum, 18.3V maxi-
CC
must be bypassed with a high quality ceramic
CC
Figure 1. Optional V
is below the UVLO threshold level.
CC
CC
CC
GND
V CC
which is high enough to trip the
OVP comparator (16.2V)
also ties internally to the
1N5246B
1N4148
1N4148
CC
PRODUCT SPECIFICATION
CC
CC
that can be applied to
current is 2mA. V
Clamp
REV. 1.2.3 11/2/04
CC
overvoltage to
CC
CC
OVP max
CC
CC
voltage
OUT
start-
pin
CC
=