FAN21SV06 Fairchild Semiconductor, FAN21SV06 Datasheet - Page 15

• Manufacturer Part Number: FAN21SV06
• Description: This part is covered in Fairchild's href="http://www
• Manufacturer: Fairchild Semiconductor

© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.1
Master/Slave Configuration
When first enabled, the IC determines if it is configured as
a master or slave for synchronization, depending on how
R
Table 2. Master / Slave Configuration
Slaves free-run in the absence of an external clock signal
input when R
regulation to be maintained. It is not recommended to
leave R
noise pick up on the clock pin.
Slave free-running frequency should be set at least 25%
lower than the incoming synchronizing pulse frequency.
Maximum synchronizing clock frequency is recommended
to be below 600KHz.
Synchronization
The
FAN21SV06 also provides the following features for
maximum flexibility.




The FAN21SV06 master outputs an 85ns-wide clock
(CLK) signal, delayed 180
This feature allows out-of-phase operation for the slaves,
thereby reducing the input capacitance requirements
when more than one converter is operating on the same
input supply. The leading SW-node edge is delayed
~40ns from the rising PWM signal.
On a slave, synchronization is rising-edge triggered. The
CLK input pin has a 1.8V threshold and a 200µA current
source pull-up.
In Master mode, the clock signals go out after power-good
signal
synchronization to an external clock signal occurs after
the power-good signal goes high. Until then, the converter
operates in free-run mode.
T
5V_Reg
is connected.
R
GND
Synchronization to an external system clock
Multiple FAN21SV06s can be synchronized to a
single master or system clock
Independently programmable phase adjustment for
one or multiple slaves
Free-running capability in the absence of system
clock or, if the master is disabled/faulted, the slaves
can continue to regulate at a lower frequency
T
synchronization
to:
Figure 34. Synchronization Timing Diagram
T
asserts
open when running in slave mode to avoid
Master / Slave
Master
Slave, free-running
T
is connected to 5V_Reg, allowing
high.
method
Likewise,
o
from its leading PWM edge.
employed
in
Slave
CLK Pin
Output
Input
by
mode
the
15
One or more slaves can be connected directly to a master
or system clock to achieve a 180
Since the synchronizing circuit utilizes a narrow reset
pulse, the actual phase delay is slightly more than 180
The FAN21SV06 is not intended for use in single-output,
multi-phase regulator applications.
PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with 2-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect AGND pin to PGND at the
output OR to the PGND plane.
Figure 37. Recommended PCB Layout
Figure 35. Slave-CLK-Input Block Diagram
Figure 36. Slaves with 180
o
phase shift.
o
Phase Shift
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o
.