RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 13

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

4.3
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Figure 3
The figure illustrates that one F pipe instruction and one M pipe instruction can be issued
concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 2 specifies
more completely the instructions within each class.
Table 2 Dual Issue Instruction Classes
Pipeline
The logical length of both the F and M pipelines is five stages with state committing (result of
instruction written back into register file) in the register write or W pipe stage. The physical
length of the floating-point execution pipeline is actually seven stages but this is completely
transparent to the user.
Figure 4 shows instruction execution within the RM7000B when instructions are issuing
simultaneously down both pipelines. As illustrated in the figure, up to ten instructions can be
executing simultaneously. This figure presents a somewhat simplistic view of the processors
operation since the out-of-order completion of loads, stores, and long latency floating-point
operations can result in there being even more instructions in process than what is shown.
Integer
add, sub, or, xor, shift,
etc.
F Pipe
FP
F Pipe IBus
Instruction Issue Paradigm
M Pipe
FP
M Pipe IBus
Instruction
Dispatch
Load/Store
lw, sw, ld, sd, ldc1, sdc1,
mov, movc, fmov, etc.
Cache
Unit
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Integer
F Pipe
Integer
M Pipe
Floating-point
fadd, fsub, fmult, fmadd,
fdiv, fcmp, fsqrt, etc.
Branch
beq, bne, bCzT, bCzF, j,
etc.
Preliminary
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