RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 31

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

4.30
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Figure 10 Processor Block Write
Figure 11 Multiple Outstanding Reads
Data Prefetch
The RM7000B supports the MIPS IV integer data prefetch (
prefetch (
language programmer when it is known or suspected that an upcoming data reference is going to
miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be
hidden under the execution of other instructions. In cases where the execution of a prefetch
instruction would cause a memory management or address error exception the prefetch is treated
as a
The “Hint” field of the data prefetch instruction is used to specify the action taken by the
instruction. The instruction can operate normally (that is, fetching data as if for a load operation)
or it can allocate and fill a cache line with zeroes on a primary data cache miss.
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Master
SysClock
SysAD
SysCmd
RspSwap*
ValidOut*
ValidIn*
Release*
PRqst*
PAck*
TcMatch
NOP
.
PREFX
Processor
Read
Addr
1
1
) instructions. These instructions are used by the compiler or by an assembly
Write
Addr
Tertiary (Miss)
NData
Data0
Data0
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
1
NData
Data1
Data1
System
3
4
2
Processor
NData
Data2
Read
Addr
NEOD
Data3
5
2
2
PREF
Tertiary (Miss)
) and floating-point data
Data0
6
Data1
7
Data0
System
NData
Preliminary
8
2
Data1
NData
24
2