RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 29

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
RM7000B. Processor requests are initiated by the RM7000B and responded to by an external
agent. External requests are issued by an external agent and require the RM7000B to respond.
The RM7000B supports one- to eight-byte transfers as well as 32-byte block transfers on the
SysAD bus. In the case of a sub-doubleword transfer, the 3 low-order address bits give the byte
address of the transfer, and the SysCmd bus indicates the number of bytes being transferred.
Handshake Signals
There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*,
are driven by an external agent to indicate to the RM7000B whether it can accept a new read or
write transaction. The RM7000B samples these signals before deasserting the address on read
and write requests.
ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the
processor to an external agent. When an external agent requires control of the bus, it asserts
ExtRqst*. The RM7000B responds by asserting Release* to release the system interface to
slave state.
PRqst* and PAck* are used to transfer control of the SysAD and SysCmd buses from the
external agent to the processor. These two pins have been added to the SysAD interface to
support multiple outstanding reads and facilitate non-blocking cache operations. When the
processor needs to reacquire control of the interface, it asserts PRqst*. The external agent
responds by asserting PAck* to return control of the interface to the processor.
RspSwap* is used by the external agent to indicate to the processor when it is returning multiple
data out of order. For example, when there are two outstanding reads, the external agent asserts
RspSwap* when it is going to return the data for the second read before it returns the data for the
first read. RspSwap* must be asserted by the external agent two cycles ahead of when it presents
data so that the processor has time to switch to the correct address for writes into the tertiary
cache.
RdType is another new pin on the interface that indicates whether a read is an instruction read or
a data read. When asserted, the reference is an instruction read. When deasserted it is a data read.
RdType is only valid during valid address cycles.
ValidOut* and ValidIn* are used by the RM7000B and the external agent respectively to
indicate that there is a valid command and data on the SysAD and SysCmd buses. The
RM7000B asserts ValidOut* when it is driving these buses with a valid command and data, and
the external agent drives ValidIn* when it has control of the system interface and is driving a
valid command and data.
System Interface Operation
To support non-blocking caches and data prefetch instructions, the RM7000B allows two
outstanding reads. An external agent may respond to read requests in whatever order it chooses
by using the response order indicator pin RspSwap*. No more than two read requests are
submitted to the external agent. Support for multiple outstanding reads can be enabled or
disabled via a boot-time mode bit. Refer to Table 16 for a complete list of mode bits.
The RM7000B can issue read and write requests to an external agent, while an external agent can
issue null and read responses to the RM7000B.
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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