RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 39

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Pin Descriptions
The following is a list of control, data, clock, tertiary cache, interrupt, and miscellaneous pins of
the RM7000B.
Table 17
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
ValidOut*
PRqst*
PAck*
RspSwap*
RdType
Pin Name
System Interface
Type
Input
Output
Input
Input
Input
Output
Output
Input
Input
Output
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Description
External request
Signals that the external agent is submitting an external request.
Release interface
Signals that the processor is releasing the system interface to slave
state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write
request.
Valid Input
Signals that an external agent is now driving a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
Valid output
Signals that the processor is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd
bus.
Processor Request
When asserted this signal requests that control of the system interface
be returned to the processor. This is enabled by Mode Bit 26.
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the
processor that it has been granted control of the system interface.
Response Swap
RspSwap* is used by the external agent to signal the processor when
it is about to return a memory reference out of order; i.e., of two
outstanding memory references, the data for the second reference is
being returned ahead of the data for the first reference. In order that the
processor will have time to switch the address to the tertiary cache, this
signal must be asserted a minimum of two cycles prior to the data itself
being presented. Note that this signal works as a toggle; i.e., for each
cycle that it is held asserted the order of return is reversed. By default,
anytime the processor issues a second read it is assumed that the
reads will be returned in order; i.e., no action is required if the reads are
indeed returned in order. This is enabled by Mode Bit 26.
Read Type
During the address cycle of a read request, RdType indicates whether
the read request is an instruction read or a data read.
Preliminary
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