RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 32

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Enhanced Write Modes
The RM7000B implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write on the SysAD bus every four
SysClock cycles. Hence for a non-block write, this meant that two out of every four cycles were
wait states.
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous data cycle. This allows for higher
SysAD bus utilization. However, at high frequencies the processor may drive a subsequent write
onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the cycle to be missed.
Write reissue mode is an enhancement to pipelined write mode and allows the processor to
reissue missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation,
the cycle is aborted by the processor and reissued at a later time.
In write reissue mode, a rate of one write every two bus cycles can be achieved. Pipelined writes
have the same two bus cycle write repeat rate, but can issue one additional write following the
deassertion of WrRdy*.
External Requests
The RM7000B can respond to certain requests issued by an external agent. These requests take
one of two forms: Write requests and Null requests. An external agent executes a write request
when it wishes to update one of the processors writable resources such as the internal interrupt
register. A null request is executed when the external agent wishes the processor to reassert
ownership of the processor external interface. Once the external agent has acquired control of the
processor interface via ExtRqst*, it can execute a null request after completing an independent
transaction between itself and system memory in a system where memory is connected directly
to the SysAD bus. Normally this transaction would be a DMA read or write from the I/O system.
Test/Breakpoint Registers
To facilitate hardware and software debugging, the RM7000B incorporates a pair of Test/Break-
point, or Watch registers, called Watch1 and Watch2. Each Watch register can be separately
enabled to watch for a load address, a store address, or an instruction address. All address
comparisons are done on physical addresses. An associated register, Watch Mask, has also been
added so that either or both of the Watch registers can compare against an address range rather
than a specific address. The range granularity is limited to a power of two.
When enabled, a match of either Watch register results in an exception. If the Watch is enabled
for a load or store address then the exception is the Watch exception as defined for the R4000 by
Cause exception code 23. If the Watch is enabled for instruction addresses then a newly defined
Instruction Watch exception is taken and the Cause code is 16. The Watch register which caused
the exception is indicated by Cause bits 25:24. Table 9 summarizes a Watch operation.
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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