RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 25

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

4.21
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Tertiary Cache
The RM7000B has direct support for an external tertiary cache. The tertiary cache is direct
mapped and block write-through with byte parity protection for data. The RM7000B tertiary
cache operates identical to the secondary cache of the RM527x while supporting additional size
increments to support 4 MB and 8 MB caches.
The tertiary interface uses the SysAD bus for data and tags while providing a separate bus,
TcLine[17:0], for addresses, along with a number of tertiary cache specific control signals.
A tertiary read looks nearly identical to a standard processor read except that the tag chip enable
signal, TcTCE*, is asserted concurrently with ValidOut* and Release*, initiating a tag probe
and indicating to the external agent that a tertiary cache access is being performed. As a result,
the external agent monitors the tertiary hit signal, TcMatch. If a hit is indicated the external
agent aborts the memory read and refrains from acquiring control of the system interface. Along
with TcTCE*, the processor also asserts the tag data enable signal, TcTDE*, which causes the
tag RAMs to latch the SysAD address internally for use as the replacement tag if a cache miss
occurs.
On a tertiary miss, a refill is accomplished with a two signal handshake between the data output
enable signal, TcDOE*, which is deasserted by the external agent, and the tag and data write
enable signal, TcCWE*, asserted by the processor. Figure 7 illustrates a tertiary cache hit
followed by a miss.
Figure 7 Tertiary Cache Hit and Miss
Other capabilities of the tertiary interface include block write, tag invalidate, and tag probe. For
details of these transactions as well as detailed timing waveforms for all the tertiary cache
transactions, refer to the RM7000 Family User Manual. The tertiary cache tag can easily be
implemented with standard components such as the Motorola MCM69T618.
Master
SysClock
SysAD
TcLine[17:0]
TcWord[1:0]
TcTCE*
TcMatch
TcDCE*
TcCWE*
TcDOE*
Processor
Index
Addr
I0
I1
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Data0
I2
Tertiary (Hit)
Data1
I3
Data2
Data3
Processor
Addr
Index
I0
I1
Tertiary (Miss)
Data0
I2
Data1
I3
Preliminary
System
Data0
I0
Data1
18
I1