RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 27

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Table 7 Cache Locking Control
Cache Management
To improve the performance of critical data movement operations in the embedded environment,
the RM7000B significantly improves the speed of operation of certain critical cache
management operations. In particular, the speed of the Hit-Writeback-Invalidate and Hit-
Invalidate cache operations has been improved, in some cases by an order of magnitude, over
that of other MIPS processors. For example, Table 8 compares the RM7000B with the R4000
processor.
Table 8 Penalty Cycles
For the Hit-Dirty case of Hit-Writeback-Invalidate in Table 8 above, if the writeback buffer is
full from some previous cache eviction, then n is the number of cycles required to empty the
writeback buffer. If the buffer is empty then n is zero.
The penalty value in Table 8 is the number of processor cycles beyond the one cycle required to
issue the instruction that is required to implement the operation.
Primary Write Buffer
Writes to secondary cache or external memory, whether cache miss write-backs or stores to
uncached or write-through addresses, use the integrated primary write buffer. The write buffer
holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache write-
back and allows the processor to proceed in parallel with memory update. For uncached and
write-through stores, the write buffer significantly increases performance by decoupling the
SysAD bus transfers from the instruction execution stream.
System Interface
The RM7000B provides a high-performance 64-bit system interface which is compatible with
the RM5200 Family. As an enhancement to the system interface, the RM7000B allows half-
Cache
Primary I
Primary D
Secondary
Operation
Hit-Writeback-
Invalidate
Hit-Invalidate
Lock
Enable
ECC[27]
ECC[26]
ECC[25]
Condition
Miss
Hit-Clean
Hit-Dirty
Miss
Hit
Set Select
ECC[28]=0→A
ECC[28]=1→B
ECC[28]=0→A
ECC[28]=1→B
ECC[28]=0→A
ECC[28]=1→B
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Penalty
RM7000B
3+n
0
3
0
2
Activate
Fill_I
Load/Store
Fill_I or
Load/Store
R4000
14+n
12
7
7
9
Preliminary
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