RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 34

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Table 10 Performance Counter Control
The performance counter interrupt only occurs when interrupts are enabled in the Status register,
IE=1, and the Interrupt Mask bit 13 (IM13) of the coprocessor 0 interrupt control register is set.
PerfControl
Field
31:11
4:0
7:5
10
8
9
Description
Event Type
Reserved (must be zero)
Count in Kernel Mode
Count in User Mode
Count Enable
Reserved (must be zero)
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
0A:
0B:
0C:
0D:
0E:
0F:
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
1B:
1C:
1D:
1E:
0:
1:
0:
1:
0:
1:
Clock cycles
Total instructions issued
Floating-point instructions issued
Integer instructions issued
Load instructions issued
Store instructions issued
Dual issued pairs
Branch prefetches
External Cache Misses
Stall cycles
Secondary cache misses
Instruction cache misses
Data cache misses
Data TLB misses
Instruction TLB misses
Joint TLB instruction misses
Joint TLB data misses
Branches taken
Branches issued
Secondary cache writebacks
Primary cache writebacks
Dcache miss stall cycles (cycles where both cache miss tokens taken and a third address is
requested)
Cache misses
FP possible exception cycles
Slip Cycles due to multiplier busy
Coprocessor 0 slip cycles
Slip cycles doe to pending non-blocking loads
Write buffer full stall cycles
Cache instruction stall cycles
Multiplier stall cycles
Stall cycles due to pending non-blocking loads - stall start of exception
Disable
Enable
Disable
Enable
Disable
Enable
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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