RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 41

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
TcLine[17:0]
TcMatch
TcTCE*
TcTDE*
TcTOE*
TcWord[1:0]
TcValid
Output
Input
Output
Output
Output
Input/Output
Input/Output
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Tertiary Cache Line Index
Tertiary Cache Tag Match
This signal is asserted by the cache Tag RAMs when a match occurs
between the value on its data inputs and the contents of the addressed
location in the RAM.
Tertiary Cache Tag RAM Chip Enable
When asserted this signal will cause either a probe or a write of the Tag
RAMs depending on the state of the Tag RAMs write enable signal.
This signal is monitored by the external agent and indicates to it that a
tertiary cache access is occurring.
Tertiary Cache Tag RAM Data Enable
When asserted this signal causes the value on the data inputs of the
Tag RAM to be latched into the RAM. If a refill of the RAM is necessary,
this latched value will be written into the Tag RAM array. Latching the
Tag allows a shared address/data bus to be used without incurring a
penalty to re-present the Tag during the refill sequence.
Tertiary Cache Tag RAM Output Enable
When asserted this signal causes the Tag RAMs to drive data onto their
I/O pins.
Tertiary Cache Double Word Index
Driven by the processor on cache hits and by the external agent on
cache miss refills.
Tertiary Cache Valid
This signal is driven by the processor as appropriate to make a cache
line valid or invalid. On Tag read operations the Tag RAM will drive this
signal to indicate the line state.
Preliminary
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