RM7000B-450T PMC-Sierra, Inc., RM7000B-450T Datasheet - Page 5

• Manufacturer Part Number: RM7000B-450T
• Description: Microprocessor, 64-Bit Data Bus, 450MHz Processor, 304-BGA
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Table of Contents
Legal Information ......................................................................................................................... 2
Contacting PMC-Sierra ................................................................................................................ 2
Revision History ........................................................................................................................... 3
1 Features ................................................................................................................................. 2
2 Block Diagram ........................................................................................................................ 3
3 Description ............................................................................................................................. 4
4 Hardware Overview ................................................................................................................ 5
Copyright ............................................................................................................................... 2
Disclaimer ............................................................................................................................. 2
Trademarks ........................................................................................................................... 2
Patents .................................................................................................................................. 2
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10 System Control Coprocessor (CP0) .............................................................................11
4.11 System Control Coprocessor Registers .......................................................................11
4.12 Virtual to Physical Address Mapping ............................................................................12
4.13 Joint TLB ......................................................................................................................13
4.14 Instruction TLB .............................................................................................................14
4.15 Data TLB ......................................................................................................................14
4.16 Cache Memory .............................................................................................................14
4.17 Instruction Cache .........................................................................................................15
4.18 Data Cache ..................................................................................................................15
4.19 Secondary Cache ........................................................................................................17
4.20 Secondary Caching Protocols ......................................................................................17
4.21 Tertiary Cache .............................................................................................................18
4.22 Cache Locking .............................................................................................................19
4.23 Cache Management .....................................................................................................20
4.24 Primary Write Buffer .....................................................................................................20
4.25 System Interface ..........................................................................................................20
4.26 System Address/Data Bus ...........................................................................................21
4.27 System Command Bus ................................................................................................21
4.28 Handshake Signals ......................................................................................................22
CPU Registers .............................................................................................................5
Superscalar Dispatch ...................................................................................................5
Pipeline ........................................................................................................................6
Integer Unit ..................................................................................................................7
ALU ..............................................................................................................................8
Integer Multiply/Divide ..................................................................................................8
Floating-Point Coprocessor ..........................................................................................9
Floating-Point Unit .......................................................................................................9
Floating-Point General Register File ............................................................................10
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary