CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 112

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

N O N - D I S C L O S U R E
LSB
A
B
C
D
0
1
2
3
4
5
6
7
8
9
E
F
MSB
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
BRSET0
BRCLR0
BRSET1
BRCLR1
BRSET2
BRCLR2
BRSET3
BRCLR3
BRSET4
BRCLR4
BRSET5
BRCLR5
BRSET6
BRCLR6
BRSET7
BRCLR7
Bit Manipulation
DIR
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BSET0
BCLR0
BSET1
BCLR1
BSET2
BCLR2
BSET3
BCLR3
BSET4
BCLR4
BSET5
BCLR5
BSET6
BCLR6
BSET7
BCLR7
DIR
1
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCS/BLO
Branch
BHCC
BHCS
REL
BRA
BRN
BCC
BNE
BEQ
BMC
BMS
BLS
BPL
BMI
BHI
BIH
BIL
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
2
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
ASL/LSL
COM
NEG
ROR
DEC
DIR
LSR
ASR
ROL
TST
CLR
INC
3
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
4
5
1
1
1
1
1
1
ASLA/LSLA
1
1
1
1
1
1
COMA
NEGA
RORA
ASRA
ROLA
DECA
LSRA
CLRA
INCA
TSTA
MUL
INH
4
Read-Modify-Write
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
11
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
ASLX/LSLX
NEGX
COMX
RORX
LSRX
ASRX
ROLX
DECX
TSTX
CLRX
INCX
INH
5
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
Table 12-7. Opcode Map
ASL/LSL
COM
NEG
ROR
ASR
ROL
DEC
CLR
LSR
TST
IX1
INC
6
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
6
6
6
6
6
6
6
6
6
5
6
A G R E E M E N T
LSB of Opcode in Hexadecimal
1
1
1
1
1
1
1
1
1
1
1
ASL/LSL
COM
NEG
ROR
DEC
LSR
ASR
ROL
TST
CLR
INC
IX
7
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
5
5
5
5
5
5
5
5
5
4
5
1
1
1
1
1
STOP
WAIT
RTS
INH
SWI
RTI
8
Control
INH
INH
INH
INH
INH
10
9
6
2
2
1
1
1
1
1
1
1
1
NOP
INH
CLC
SEC
RSP
TXA
TAX
CLI
SEI
9
INH
INH
INH
INH
INH
INH
INH
INH
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LSB
CMP
IMM
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
BSR
LDA
LDX
BIT
A
0
MSB
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
REL
IMM
2
2
2
2
2
2
2
2
2
2
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
BRSET0
CMP
AND
EOR
ADC
ORA
ADD
DIR
SUB
SBC
CPX
LDA
JMP
JSR
LDX
STX
STA
BIT
B
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Register/Memory
MSB of Opcode in Hexadecimal
Number of Cycles
Opcode Mnemonic
Number of Bytes/Addressing Mode
CMP
EXT
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
JMP
R E Q U I R E D
LDA
STA
JSR
LDX
STX
BIT
C
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
4
4
4
4
4
4
4
5
4
4
4
4
3
6
4
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
LDA
JMP
JSR
LDX
STX
IX2
STA
BIT
D
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
5
5
5
5
5
5
5
6
5
5
5
5
4
7
5
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
JMP
LDX
STX
LDA
STA
JSR
IX1
BIT
E
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
4
4
4
4
4
4
4
5
4
4
4
4
3
6
4
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
STA
JMP
JSR
LDX
STX
BIT
IX
F
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
MSB
A
B
C
D
E
0
1
2
3
4
5
6
7
8
9
F
LSB