CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 33

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

3.3.3 Program Counter
3.3.4 Stack Pointer
3.3.5 Condition Code Register
MC68HC05C4A
MOTOROLA
—
Rev. 4.0
The program counter (PC) is a 13-bit register that contains the address
of the next byte to be fetched.
The stack pointer (SP) contains the address of the next free location on
the stack. During an MCU reset or the reset stack pointer (RSP)
instruction, the stack pointer is set to location $00FF. The stack pointer
is then decremented as data is pushed onto the stack and incremented
as data is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are
permanently set to 0000011. These eight bits are appended to the six
least significant register bits (LSB) to produce an address within the
range of $00FF to $00C0. Subroutines and interrupts may use up to 64
(decimal) locations. If 64 locations are exceeded, the stack pointer
wraps around and loses the previously stored information. A subroutine
call occupies two locations on the stack; an interrupt uses five locations.
The condition code register (CCR) is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed, and the fifth
bit indicates whether interrupts are masked. These bits can be tested
individually by a program, and specific actions can be taken as a result
of their state. Each bit is explained in the following paragraphs.
H — Half Carry
I — Interrupt
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the interrupt bit is cleared.
Central Processor Unit (CPU)
General Release Specification
Central Processor Unit (CPU)
CPU Registers
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