CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 47
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CM68HC05C4ACFB
Manufacturer Part Number
CM68HC05C4ACFB
Description
Microcontroller
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.CM68HC05C4ACFB.pdf
(156 pages)
- Current page: 47 of 156
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6.4 Stop Recovery
6.5 Wait Mode
MC68HC05C4A
MOTOROLA
NOTES:
1.
2.
3.
INTERNAL ADDRESS BUS
Represents the internal gating of the OSC1 pin
IRQ pin edge-sensitive option
IRQ pin level and edge sensitive option
—
Rev. 4.0
INTERNAL CLOCK
unaltered. All input/output lines remain unchanged. The processor can
be brought out of stop mode only by an external interrupt or reset.
The processor can be brought out of stop mode only by an external
interrupt or reset. See
The WAIT instruction places the MCU in a low-power consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the timer, SCI, SPI, and the oscillator
remain active. Any interrupt or reset will cause the MCU to exit wait
mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
OSC1
RESET
Figure 6-2. Stop Recovery Timing Diagram
IRQ
IRQ
1
3
2
Low-Power Modes
t
t
ILIH
RL
t
ILCH
Figure
6-2.
1FFE
4064 t cyc
1FFE
1FFE
INTERRUPT ($1FFA, $1FFB)
RESET ($1FFE, $1FFF) OR
General Release Specification
VECTOR FETCH
1FFE
1FFF
Low-Power Modes
Stop Recovery
47
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