CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 37

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

4.3 Hardware Controlled Interrupt Sequence
4.4 Software Interrupt (SWI)
MC68HC05C4A
MOTOROLA
—
Rev. 4.0
Three functions (RESET, STOP, and WAIT) are not in the strictest sense
interrupts; however, they are acted upon in a similar manner. Flowcharts
for hardware interrupts are shown in
The software interrupt (SWI) is an executable instruction and a non-
maskable interrupt. It is executed regardless of the state of the I bit in the
CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts
which were pending when the SWI was fetched but before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $1FFC and
$1FFD.
1. RESET — A low input on the RESET input pin causes the program
2. STOP — The STOP instruction causes the oscillator to be turned
3. WAIT — The WAIT instruction causes all processor clocks to stop,
to vector to its starting address, which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset, as previously described in
Section 5.
off and the processor to “sleep” until an external interrupt IRQ) or
reset occurs.
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ),
serial periferal interface, serial communications interface, or timer
interrupt. These individual interrupts have no special wait vectors.
Resets.
Interrupts
Figure
Hardware Controlled Interrupt Sequence
4-1.
General Release Specification
Interrupts
37