CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 86

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

Serial Peripheral Interface (SPI)
10.6 SPI Registers
General Release Specification
86
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
MASTER MCU
SPI SHIFT REGISTER
SPDR ($000C)
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3
interconnections.
Three registers in the SPI provide control, status, and data storage
functions. These registers are called the serial peripheral control register
(SPCR), serial peripheral status register (SPSR), and serial peripheral
data I/O register (SPDR) and are described in the following paragraphs.
I/O PORT
Serial Peripheral Interface (SPI)
illustrates the MOSI, MISO, SCK, and SS master-slave
PD3/MOSI
PD2/MISO
PD4/SCK
PD5
SS
SPI SHIFT REGISTER
SLAVE MCU
SPDR ($000C)
MC68HC05C4A
MOTOROLA
—
Rev. 4.0