T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet

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... CelXpres ™ T8207 ATM Interconnect 1 Product Overview 1.1 Features > OC-3 transport capability UTOPIA level 1 and 2 (8-bit) cell-level handshake interface (ATM or PHY layers) 32 multi-PHY (MPHY) operation Shared UTOPIA mode Egress SDRAM buffer support to expand UTOPIA output priority queues for 32K to 512K cells: — 64 queues configurable up to four queues per PHY with programmable sizes — ...

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... Incoming UTOPIA Cell Interface .............................................................................................................43 9.1.1 Incoming PHY Mode (Cells Received by T8207) .......................................................................43 9.1.2 Incoming ATM Mode (Cells Received by T8207).......................................................................43 9.2 Outgoing UTOPIA Cell Interface .............................................................................................................44 9.2.1 Outgoing PHY Mode (Cells Sent by T8207)...............................................................................44 9.2.2 Outgoing ATM Mode (Cells Sent by T8207) ..............................................................................45 9.3 Counters..................................................................................................................................................46 9.4 55-Byte UTOPIA Mode............................................................................................................................47 9.5 Shared UTOPIA Mode ............................................................................................................................48 9.6 UTOPIA Pin Modes .................................................................................................................................50 9.7 UTOPIA Clocking ...

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... Electrical Characteristics .................................................................................................................. 144 19 Timing Requirements...................................................................................................................................... 145 19.1 Microprocessor Interface Timing........................................................................................................... 146 19.2 UTOPIA Timing..................................................................................................................................... 152 19.3 External LUT Memory Timing ............................................................................................................... 153 19.4 Cell Bus Timing..................................................................................................................................... 155 19.5 SDRAM Interface Timing ...................................................................................................................... 156 20 Outline Diagram.............................................................................................................................................. 157 21 Ordering Information....................................................................................................................................... 158 Agere Systems Inc. Table of Contents (continued) CelXpres T8207 ATM Interconnect Page 3 ...

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... CelXpres T8207 ATM Interconnect Figure Figure 1. Functional Block Diagram ......................................................................................................................... 9 Figure 2. Dual Bus Implementation ........................................................................................................................ 10 Figure 3. 272-Pin PBGA—Top View ...................................................................................................................... 19 Figure 4. Translation RAM Memory Map—8-Byte Records, for Ports ..................................................... 29 Figure 5. Translation RAM Memory Map—8-Byte Records, for Greater than 16 Ports...........................................30 Figure 6. Translation Record Types— ...

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... Table 16. Port Numbering for MPHY Configurations ............................................................................................ 51 Table 17. Supported Memory Configurations ....................................................................................................... 64 Table 18. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 1 ................. 67 Table 19. Queue Organization and Port Group Address/Priority Bits for 32 Ports ................................................ 69 Table 20. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 0................... 71 Table 21 ...

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... CelXpres T8207 ATM Interconnect Table Table 49. GPIO Input Value (GPIO_IV) (3Dh)........................................................................................................ 90 Table 50. Control Cell Receive Direct Memory (CCRXDM) (60h to 93h)............................................................... 91 Table 51. Control Cell Transmit Direct Memory (CCTXDM) (A0h to D7h) ............................................................. 91 Table 52. PHY Port 0 and Control Cells Multicast Direct Memory (PP0MDM) (E0h to FFh) ................................. 92 Table 53 ...

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... Table 145. External LUT Memory Write Timing (cyc_per_acc = 2) .................................................................... 154 Table 146. External LUT Memory Write Timing (cyc_per_acc = 3) .................................................................... 154 Table 147. Cell Bus Timing ................................................................................................................................. 155 Table 148. SDRAM Interface Timing .................................................................................................................. 156 Agere Systems Inc. Table of Contents (continued) CelXpres T8207 ATM Interconnect Page 7 ...

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... The T8207 may be configured as an ATM or PHY level device providing cell routing between UTOPIA and a 32-bit wide cell bus. In addition to the 32 data signals, the bus has the following signals: ...

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... CELLS) TX UTOPIA TX PHY CELL BUFFER FIFO (128 CELLS) (128 CELLS) CELL BUS INPUT FIFO (4 CELLS) SDRAM INTERFACE 1M TO 16M x 16 SDRAM Figure 1. Functional Block Diagram CelXpres T8207 ATM Interconnect CELL BUS ARBITER CELL BUS CELL BUS INTERFACE CELL BUS MONITORING 5-7542E (F) 9 ...

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... Product Overview (continued) Figure 2 illustrates the use of the CelXpres T8207 in a system with dual backplane cell buses using shared UTOPIA mode. In this configuration, both T8207 devices on each card receive cells from the UTOPIA bus, and each device uses its translation table to determine if the cell should be transmitted on its backplane cell bus. In the egress direction, each T8207 device receives cells from its cell bus to transmit on the UTOPIA bus ...

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... To set is to change one or multiple bit values to ‘1.’ All memory addresses are specified in hexadecimal. Addresses are converted from bytes to words or double words using the little-endian format, unless otherwise specified. A signal name with a trailing asterisk is active-low, e.g., sd_we*. Bits will be designated bits (y:x). Agere Systems Inc. CelXpres T8207 ATM Interconnect 11 ...

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... Last 4 bytes of the cell bus frame. The grant section occurs during the last clock cycle of the cell bus frame. During this cycle, the cell bus arbiter indicates which T8207 may transmit during the next bus cell unit of the cell bus frame. A parity vector is also transmitted during the grant section. ...

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... Advance Data Sheet September 2001 2 Pin Description This section defines the CelXpres T8207 pins. All TTL compatible inputs or I/O are 5 V tolerant. No GTL+ inputs or I/O are 5 V tolerant. Table 1. UTOPIA Pins Symbol Ball u_rxaddr[4:0] R2, P3, R1, P2, P1 u_rxdata[7:0] V2, U3, T4, V1, U2, T3, U1, T2 u_rxclk T1 u_rxsoc ...

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... CelXpres T8207 ATM Interconnect 2 Pin Description (continued) Table 2. Cell Bus Pins Symbol Ball ua*[4:0] B18, B17, C17, D16, A18 cb_d*[31:0] B5, C6, D7, A5, B6, C7, A6, B7, A7, C8, B8, A8, D9, C9, B9, A9, A11, C11, B11, A12, B12, C12, D12, A13, B13, C13, A14, B14, C14, A15, B15, ...

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... Long printed- wiring board traces should have 50 — I SDRAM Current Reference. Precision current reference for SDRAM buffers resistor must be connected between this pin and GND. CelXpres T8207 ATM Interconnect Name/Description impedance matching buffers. nominal nominal impedance. impedance matching buffers. Long ...

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... CelXpres T8207 ATM Interconnect 2 Pin Description (continued) Table 4. Microprocessor Interface Pins Symbol Ball a[7:1] W6, Y6, V7, W7, Y7, V8, W8 a[0]/ale Y8 d[7:0] U9, V9 W9, Y9, W10, V10, Y10, Y11 sel* W12 wr*_ds* V12 rd*_rw* U12 int_irq* Y12 rdy_dtack* U11 mot_sel Y13 mux W13 16 Reset Type Value — ...

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... This pin has an internal 50 k pull-up resistor. — I Test Clock (JTAG). TTL compatible input tolerant. This pin has an internal 50 k — I Test Mode Select (JTAG). TTL compatible input toler- ant. This pin has an internal 50 k pull-up resistor. CelXpres T8207 ATM Interconnect Name/Description Name/Description pull-up resistor. 17 ...

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... CelXpres T8207 ATM Interconnect 2 Pin Description (continued) Table 7. General-Purpose Pins Symbol Ball gpio[7:0] U5, Y3, Y4, V5, W5, Y5, V6, U7 reset* V14 xtalin V13 xtalout Y14 cko W11 cko_e V11 NC A2, A3, A16, B2, B3, B4, C3, C4, C5, D5, U16, V3, V4, V17, V18, W1, W2, W3, W4, W18, W19, Y1, Y2, Y15, ...

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... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VSS VDD VSS Figure 3. 272-Pin PBGA—Top View CelXpres T8207 ATM Interconnect VDD VSS VDD VSS VDD VSS VDD VDD VSS ...

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... The device is now in the reset state, and the following start-up procedure must be executed to ensure proper oper- ation: 1. After pclk (xtalin) is provided to the T8207, and the device is in the reset state: A. Write the mclk PLL configuration 0 and 1 registers at addresses 2Ah and 2Bh. B. Continue after the PLL has stabilized in 100 s. ...

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... During hot insertion, the cell bus is not corrupted because the GTL+ outputs high-impedance state during the powerup reset. Therefore, proper timing should be met in the external powerup reset circuit. Agere Systems Inc. CelXpres T8207 ATM Interconnect 21 ...

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... The bypass PLL (bypb) and PLL enable (pllen) bits are used to select the source of mclk for the T8207. To select the output of the PLL as the clock, both bits must be programmed to ‘1,’ and to select pclk as the clock, both bits must be programmed to ‘ ...

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... In Intel mode, the rd*_rw* input is an active-low read enable signal, and wr*_ds active-low write enable sig- nal. A logic low level on rd*_rw* indicates to the T8207 that the current access is a read, and a logic low level on wr*_ds* indicates the access is a write. Finally, the rdy_dtack* output is an active-high ready signal. The T8207 asserts this signal high when a microprocessor access is complete ...

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... Only the most significant 25 bits are supplied to the extended mem- ory address registers (addresses 30h—34h). The following procedure outlines the steps needed for extended memory accesses in the T8207 device. 6.3.1.1 Extended Memory Writes 1 ...

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... Microprocessor Interface 6.3.2 CelXpres T8207 Access Performance The times represented in the following table reflect access times for various microprocessor interface reads and writes. For direct access registers, the values represent the time until the rdy_dtack signal transitions indicating the data transfer portion of the access is complete. For accesses to extended memory, the values represent the time from the completion of a write to register 34h until the ext_strt_acc bit is cleared ...

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... General-Purpose I/O (GPIO) The T8207 has eight programmable general-purpose I/O pins called GPIO. These GPIO pins may be indepen- dently programmed, via the GPIO_oe[7:0] bits in the GPIO output enable register (address 39h inputs or outputs GPIO_oe bit is set to ‘1,’ the corresponding GPIO pin is an output cleared to ‘0,’ the correspond- ing GPIO pin is an input ...

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... RAM addresses. The tram_size configuration bits, also in the main configu- ration 1 register, are used to select memory sizes of 32 Kbytes, 64 Kbytes, 128 Kbytes, or 256 Kbytes. Therefore, the maximum look-up table size of 512 Kbytes is realized when two RAM chips of 256 Kbytes each are used. Agere Systems Inc. CelXpres T8207 ATM Interconnect 27 ...

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... CelXpres T8207 ATM Interconnect 8 Look-Up Table (continued) 8.2 Organization Organization is discussed in terms of 8-byte records. Differences in organization for 8-byte records and 16-byte records will be discussed in Section 8.4, Extended Records. The look-up table may be configured to support ports when multi-PHY mode is used, effectively creating a separate look-up table for each port. ...

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... VP OAM VCI = 31 (F4) +0100h VP OAM VCI = 6 & “110” (F4) (RM-VPC) +0108h VC OAM PTI = “100” (F5) +0110h VC OAM PTI = “101” (F5) +0118h VC OAM PTI = “110” (F5) +0120h VC OAM PTI = “111” (F5) +0128h RESERVED +0130h RESERVED +01F8h RESERVED CelXpres T8207 ATM Interconnect 29 ...

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... CelXpres T8207 ATM Interconnect 8 Look-Up Table (continued) ROUTING LOOK-UP MEMORY MAP 0000h OAM CELL ROUTING PORT 0 AND 1 0200h OAM CELL ROUTING PORT 2 AND 3 0400h OAM CELL ROUTING PORT 4 AND 5 0600h OAM CELL ROUTING PORT 6 AND 7 0800h OAM CELL ROUTING PORT 8 AND 9 ...

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... VCI TRANSLATION RECORD b11 b10 VCI[15:0] CELL BUS ROUTING HEADER[15:0] TANDEM ROUTING HEADER[15:0] OAM/RM TRANSLATION RECORD b11 b10 VCI[15:0] CELL BUS ROUTING HEADER[15:0] TANDEM ROUTING HEADER[15:0] Action CelXpres T8207 ATM Interconnect VPI[11: ...

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... CelXpres T8207 ATM Interconnect 8 Look-Up Table (continued) Enable OAM/RM Routing (E). When this bit is ‘1’ in the VPI record and the VCI is less than 32, the routing and translation information is obtained from the appropriate OAM/RM F4 record. If this bit is ‘1’ in the VCI record and the most significant bit of the PTI in the cell header is ‘ ...

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... Port’s OAM base address plus 108h “101” Port’s OAM base address plus 110h “110” Port’s OAM base address plus 118h “111” Port’s OAM base address plus 120h Agere Systems Inc. OAM Translation Offset CelXpres T8207 ATM Interconnect 33 ...

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... CelXpres T8207 ATM Interconnect 8 Look-Up Table (continued) Next, the validity of the F5 OAM record is determined by checking its A and I bits valid, the cell is routed as described by the OAM routing control (C1, C0) bits. (See the definition for these bits in Section 8.2, Organization.) If the E bit in the VCI record is not one or if the C1 and C0 bits in the OAM record are zero and one, respectively, the cell does not receive OAM routing. If the cell is not routed as an OAM cell, information in the VCI translation record is used to route the cell. The cell’ ...

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... VPI/VCI TRANSLATION; ROUTING FROM OAM RECORD VPI/VCI PRESERVED; ROUTING FROM OAM RECORD VPI TRANSLATION; ROUTING FROM VP RECORD Figure 7. Translation RAM Flow Diagram CelXpres T8207 ATM Interconnect VCI READ VCI FROM ATM CELL HEADER NO CELL VCI IN DISCARDED RANGE? YES READ VCI RECORD ...

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... CelXpres T8207 ATM Interconnect 8 Look-Up Table (continued) 8.4 Extended Records The length of the translation records may be extended to 16 bytes to support two cell counts for each translation record. The lut_rec_form bits in the extended LUT configuration register (address 011Eh) are used to select this extended mode. In extended (16-byte) mode, two 32-bit counters are appended to the 8-byte records. ...

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... SPECIAL CELL COUNT[15:0] EXTENDED OAM/RM TRANSLATION RECORD b11 b10 VCI[15:0] CELL BUS ROUTING HEADER[15:0] TANDEM ROUTING HEADER[15:0] TOTAL CELL COUNT[31:16] TOTAL CELL COUNT[15:0] SPECIAL CELL COUNT[31:16] SPECIAL CELL COUNT[15:0] CelXpres T8207 ATM Interconnect VPI[11: ...

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... CelXpres T8207 ATM Interconnect 8 Look-Up Table (continued) Because the translation records are larger in extended mode, the look-up table memory map changes, the transla- tion record address calculations change, and the memory size calculations change. Figure 9 shows the new trans- lation RAM memory map for 16-byte records when the device is configured for 16 or less PHY ports. When greater than 16 PHY ports are used, the look-up table is shared between even and odd ports ...

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... VP OAM VCI = 31 (F4) +0200h VP OAM VCI = 6 & “110” (F4) (RM-VPC) +0210h VC OAM PTI = “100” (F5) +0220h VC OAM PTI = “101” (F5) +0230h VC OAM PTI = “110” (F5) +0240h VC OAM PTI = “111” (F5) +0250h RESERVED +0260h RESERVED +03F0h RESERVED CelXpres T8207 ATM Interconnect 39 ...

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... CelXpres T8207 ATM Interconnect 8 Look-Up Table (continued) To calculate the 16-byte translation record address for the F4 type OAM cell, the incoming VCI is multiplied by 16, and the resulting product is added to the port’s OAM base address. For the special case when the incoming VCI is six and the PTI in the cell header is “ ...

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... Diagnostics The T8207 also includes diagnostics to track misrouted cells. A cell is considered misrouted if its A and I bits are “00,” if its VCI is out of range the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in the incoming cell header are not all zero (see Section 8.3, Look-Up Procedure). When a misrouted cell is detected, the misrouted cell header high and low registers (addresses 0146h and 0148h) may be updated ...

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... In PHY mode, the T8207 functions as a single PHY device on the UTOPIA bus or as one of 31 PHY devices on the UTOPIA level two bus. In addition to the required UTOPIA signals, the T8207 supports an additional three transmit and three receive enable (u_txenb*[3:1] and u_rxenb*[3:1]) signals, an additional three transmit and three receive cell available (u_txclav[3:1] and u_rxclav[3:1]) signals, a transmit parity (u_txprty) signal, and a receive parity (u_rxprty) signal ...

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... When the T8207 device is in PHY mode, if bit 5 (dont_inhibit_rxphy_clav) of register 0112h is cleared to ‘0,’ the rx_clav signal is deasserted if the RX UTOPIA FIFO is considered full. If this bit is set to ‘1,’ the T8207 keeps the rx_clav signal always asserted high indicating the capability to accept cells even if the RX UTOPIA FIFO could overrun actually overrun ...

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... ATM layer’s RxEnb* signal, and the u_txclav[0] signal is an output connected to the ATM layer’s RxClav signal PHY device, the T8207 may use queue group 0 (queues and 3) in the SDRAM and TX UTOPIA cell buffer. The div_queue bits in the main configuration 2 register (address 0112h) may be programmed to “ ...

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... If the T8207_sel bit in the main configuration 2 register, Table 59, is set, each port is assigned four queues in the TX UTOPIA cell buffer except in the case of 32 ports. For 32 ports, each port is assigned two queues. Each group of four queues is priority encoded where the lowest-numbered queue has the highest priority ...

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... UTOPIA Interface (continued) If the T8207_sel bit is set and 16 or less ports are used, then each port uses four queues with priorities from where 0 is the highest priority and 3 is the lowest priority. The lowest-numbered queue in the group of four is assigned priority 0, and the highest-numbered queue in the group is assigned priority 3. For 32 PHY ports, any of the four queues in each group may be assigned to either the even- or odd-numbered port ...

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... UTOPIA Mode In this special UTOPIA mode, the T8207 transmits a 55-byte cell, as opposed to 53 bytes, on the UTOPIA bus. The extra 2 bytes are the tandem routing header received with the cell from the cell bus. These 2 bytes are appended to the beginning of the cell with the tandem routing header [15:8] byte first, followed by the tandem routing header [7:0] byte ...

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... Shared UTOPIA Mode The shared UTOPIA mode supports PHY ports using only 32 queues, and it allows two T8207 devices on different cell buses to share the same UTOPIA bus. This shared mode can be used to provide redundancy or to increase the cell bus system capacity. One T8207 device is configured as master and the other as slave, using the slave_en bit in the main configuration/control register (address 0110h) ...

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... Advance Data Sheet September 2001 9 UTOPIA Interface (continued) U_TXCLK * U_TXENB U_TXSOC U_TXDATA[7:0] P44 P45 P46 U_TXPRTY GRANT QS[4] REQUEST Agere Systems Inc. P47 VALID QS[3] QS[2] QS[1] QS[0] R[0] INVALID Figure 13. TX UTOPIA Bus Sharing CelXpres T8207 ATM Interconnect P46 P47 X QR0 QR1 QR2 INVALID 5-7786aF 49 ...

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... UTOPIA level one devices. Use this selection to connect from one to four PHY devices to the T8207 in ATM mode. If only one PHY is connected, any of the four cell available signals may be con- nected to the PHY. For two PHY devices, connect any two (internal port number must be matched to the clav being used) ...

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... CelXpres T8207 ATM Interconnect Port 4 Port 5 Port 6 enb*[2], — enb*[3], clav[2], clav[3], addr = 0 addr = 0 enb*[1], — enb*[1], clav[1], clav[1], addr = 0 addr = 2 enb*[1], ...

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... CelXpres T8207 ATM Interconnect 9 UTOPIA Interface (continued) Table 16. Port Numbering for MPHY Configurations (continued addr clav/enb* Port — — — — — — — enb*[1], clav[1], addr = 0 addr = addr clav/enb* Port 24 ...

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... UTOPIA Clocking All TX UTOPIA signals in the T8207 are clocked on the rising edge of the TX UTOPIA clock, and all RX UTOPIA signals are clocked on the rising edge of the RX UTOPIA clock. The UTOPIA specifications state that the ATM layer supplies the transmit and receive UTOPIA interface clocks to the PHY layers ...

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... The acknowledge (cb_ack*) signal is used to acknowledge the successful receipt of a cell. This signal is asserted low during the next request cycle by the T8207 that receives the cell. This signal is not asserted for multicast or broadcast cells. In the event of an overflow in the control cell RX FIFO, the loopback FIFO, the TX PHY FIFO, or the cell bus input FIFO, the acknowledge signal will assert low ...

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... Transmission grants for the next frame are always given at the end of the current frame. Cells to be transmitted onto the cell bus come from three sources internal to the T8207. Data cells from the UTOPIA bus are placed in the RX PHY FIFO to await transmission onto the cell bus. Control cells from the micro- processor wait in the control cell TX FIFO, and loopback cells from the cell bus wait in the loopback FIFO ...

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... CelXpres T8207 ATM Interconnect 10 Cell Bus Interface (continued) 10.2 Cell Bus Frames A cell bus frame is always 16 clock cycles. The cell bus frame has three sections (request, bus cell, and grant). During the request section, which is the first clock cycle of the frame, 16 devices assert their transmission requests onto the bus ...

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... PAYLOAD BYTE 34 PAYLOAD BYTE 37 PAYLOAD BYTE 38 PAYLOAD BYTE 41 PAYLOAD BYTE 42 PAYLOAD BYTE 45 PAYLOAD BYTE 46 — — — — — — — — — — — — — — — — — CelXpres T8207 ATM Interconnect TANDEM ROUTING HEADER VCI[15:0] ...

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... CelXpres T8207 ATM Interconnect 10 Cell Bus Interface (continued) Devices on the cell bus make their requests during the first cycle of each frame. In 16-user mode, each device asserts a request every frame. In 32-user mode, each device asserts a request every two frames. In 32-user mode, devices with unit addresses 0 through 15 assert their requests during the even frames, and devices with unit addresses 16 through 31 assert their requests during the odd frames ...

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... Control cells accepted from the cell bus are routed to the control cell RX FIFO. The microprocessor connected to the T8207 reads the control cell at the head of the FIFO using the control cell receive direct memory at addresses 60h to 93h (or extended memory at addresses 0800h to 0832h). After the microprocessor reads the cell, it sets the cntl_cell_rd bit in the main configuration/control register (address 0110h) to remove the cell from the head of the FIFO ...

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... T8207 (device second T8207 (device 2). The second T8207 (device 2) returns the cell to the first T8207 (device 1), or, if desired, the second T8207 (device 2) may send the cell on to one or more entirely different T8207 devices. Device 2 accepts the loopback cell and replaces the most significant 12 bits of the cell bus routing header with the routing_header bits in its loopback register (address 0118h) ...

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... For ATM mode, if the T8207_sel bit (Table 59) is set, and 16 PHY ports or less are being used, the broadcast data cells are transmitted to all the ports ports are used, the broadcast data cells are transmitted to only 16 of the 32 ports depending on the cell priority bits that select the specific queue ...

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... Cell Bus Monitoring Every T8207 device monitors the cell bus for proper operation. The monitoring section of the T8207 checks for the presence of the read clock, the write clock, and the frame synchronization signal. The cb_wc_miss bit in the main interrupt status 1 register (address 0102h) is set when the write clock is inactive for 32 mclk cycles. Likewise, the cb_rc_miss bit in the main interrupt status 1 register is set when the read clock is inactive for 32 mclk cycles ...

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... When the clock source is centrally located among the cell bus devices, a longer delay may be used. When the clock source is at either end of the cell bus devices, a shorter delay is needed. Also, a higher clock fre- quency requires a shorter delay. Agere Systems Inc. CelXpres T8207 ATM Interconnect 63 ...

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... Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207). This cell buffer holds 128 outgoing cells. Additional buffering is provided by an exter- nal SDRAM. Connection to an external SDRAM is selected by clearing the sdram_bypass bit in the main configura- tion 1 register (address 0100h) ...

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... SDRAM Interface Timing The mclk clock is the source of the SDRAM clock (sd_clk) from the T8207. Based on the frequency of the SDRAM clock and the speed grade of the SDRAM, four timing parameters must be programmed into the SDRAM configu- ration register at address 0408h. These timing parameters are specified in SDRAM (mclk) clock cycles and are listed below: RAS inactive to CAS active (ras2cas)— ...

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... Likewise, PHY port 2 is assigned group one or queues four, five, six, and seven, and so on. An ATM configured to support 16 PHY ports is a special case. When the T8207_sel bit is set and the ATM is con- figured to support 16 PHY ports, each port (0—15) is assigned to its associated queue group as illustrated in Table 18, regardless of the value of the port_rte[63:0] bits ...

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... Advance Data Sheet September 2001 11 SDRAM Interface (continued) Table 18. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 1 Port Number Queue Group Queue Number ...

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... CelXpres T8207 ATM Interconnect 11 SDRAM Interface (continued) Table 18. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 1 (continued) Port Number Queue Group Queue Number ...

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... High 35 Low 36 High 38 Low 37 High 39 Low 40 High 42 Low CelXpres T8207 ATM Interconnect Priority Bits “0000” “00” “0000” “10” “0000” “01” “0000” “11” “0001” “00” “0001” “10” “0001” “01” ...

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... CelXpres T8207 ATM Interconnect 11 SDRAM Interface (continued) Table 19. Queue Organization and Port Group Address/Priority Bits for 32 Ports (continued) Port Number Queue Group ...

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... Advance Data Sheet September 2001 11 SDRAM Interface (continued) Table 20. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 0 Port Number Queue Group Queue Number ...

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... SDRAM Refresh The T8207 SDRAM interface performs CAS before RAS (CBR) refresh commands at a rate programmed in the ref_cnt bits of the refresh register (address 0410h). The value in the refresh register represents refresh cycles in SDRAM clock cycles. One refresh command is executed every ref_cnt clock cycles, on average, when the SDRAM is idle ...

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... This is a worst-case example and assumes that all potential cells on the cell bus are going to this one device. The SDRAM frequency calculation produces a lower frequency if the actual system characteristics are considered and if the distribution of cells is controlled. Agere Systems Inc. = 151 Kcells per second. CelXpres T8207 ATM Interconnect 73 ...

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... T8207 sets the EFCI bit in cells that leave a queue that is filled beyond the limit programmed in the fecn_fillX[24:9] and fecn_fillX[8:6] bits in Table 119. (See Figure 12.) The T8207 only sets the EFCI bit in cells when the function is enabled by the queueX_fecn_en bit in the queue X registers (address 0440h through 04BEh). When a received cell exceeds the FECN fill level for a queue, the T8207 sets the corresponding queueX_fecn_lim status bit in the queue X registers ...

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... Places the boundary-scan register in extest mode. SAMPLE “001” Places the boundary-scan register in sample mode. Reserved “010”—“110” Reserved. BYPASS “111” Places the bypass register in the scan chain. Agere Systems Inc. CelXpres T8207 ATM Interconnect Description 75 ...

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... CelXpres T8207 ATM Interconnect 13 JTAG Test Access Port 13.2 Boundary-Scan Register The boundary-scan register (BSR) is 222 bits in length. Table 22 gives descriptions of each cell in the boundary- scan chain beginning with the least significant bit. Table 22. Boundary-Scan Register Descriptions Boundary-Scan Name Register Bit 0—4 ...

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... Bidirectional. — U_RXADD(4:0) are inputs when U_RXADDR_OE = 0. u_rxaddr[0:4] Bidirectional. — U_RXCLV0 is an input when U_RXCLAV0_OE = 0. u_rxclav[0] Bidirectional. u_rxclav[1:3] Input. — U_RXCLK is an input when U_RXCLK_OE = 0. T1 Bidirectional. u_rxdata[0:7] Input. — U_RXENB( input when U_RXENB0_OE = 0. CelXpres T8207 ATM Interconnect Description 77 ...

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... CelXpres T8207 ATM Interconnect 13 JTAG Test Access Port . Table 22 Boundary-Scan Register Descriptions (continued) Boundary-Scan Name Register Bit 180 U_RXENB(0) 181 U_RXENB_OE 182—184 U_RXENB(1) – U_RXENB(3) 185 U_RXPRTY 186 U_RXSOC 187 U_SHR_I 188 U_SHR_O_OE 189 U_SHR_O 190 U_TXADDR_OE 191—195 U_TXADD(0:4) ...

Page 79

... September 2001 14 Registers The T8207 has two distinct memory spaces, which are the direct memory access registers and the extended mem- ory registers. The direct memory access registers are directly addressed 8-bit (byte) registers and are mapped between addresses 00h and FFh. The extended memory registers are indirectly addressed and mapped between addresses 0100h and 3FFFFFEh ...

Page 80

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 23. Register Map (continued) Register Name GPIO Input Value (GPIO_IV) Control Cell Receive Direct Memory (CCRXDM) Control Cell Transmit Direct Memory (CCTXDM) PHY Port 0 and Control Cells Multicast Direct Memory (PP0MDM) Main Configuration 1 (MCF1) Main Interrupt Status 1 (MIS1) ...

Page 81

... PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) PHY Port X Multicast Memory (PPXMM) PPD Memory (PPDM) Queue X Definition Structure (QXDEF) Translation RAM Memory (TRAM) SDRAM (SDRAM) Agere Systems Inc. CelXpres T8207 ATM Interconnect Address (h) Reference Page 0210h 123 0212h 124 ...

Page 82

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.2 Direct Memory Access Registers The direct memory access registers are the only registers that can be directly addressed. These registers provide some status and initial control of the device. In addition, the direct memory access register set includes some extended memory access registers, which are used to indirectly access the extended memory registers. All unde- fined addresses in the direct memory access registers’ ...

Page 83

... Big Endian. If this bit is ‘0,’ register fields in the direct address space, 30h to 37h, will be in little-endian format. If ‘1,’ fields in the direct address space, 30h to 37h, will be in big-endian format. 0 Reserved. These bits must be programmed to ‘0.’ CelXpres T8207 ATM Interconnect Description 83 ...

Page 84

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 28. Interrupt Service Request (ISREQ) (29h) Name Bit Pos. Type Reserved 0 RO int_serv_mainreg 1 RO int_serv_sdramreg 2 RO int_serv_utopiareg 3 RO Reserved 4 RO ctrl_cell_sent_sr 5 RO ctrl_cell_av_sr 6 RO Reserved 7 RO Table 29. mclk PLL Configuration 0 (MPLLCF0) (2Ah) Name Bit Pos. Type ...

Page 85

... Under this condition, no cells can be transmitted to the back- plane. When this bit is set to ‘1,’ the GTL+ transmitters are powered up and cells are transmitted to the backplane Reserved. Program to ‘0.’ Reserved. Program to ‘1.’ Reserved. Program to ‘0.’ CelXpres T8207 ATM Interconnect Description Description Description 85 ...

Page 86

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access Registers 30h—37h Table 33. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h) Name Bit Pos. Type Reset Reserved 4:0 RO ext_a[8:6] 7:5 RW Table 34. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h) Name Bit Pos. Type ...

Page 87

... Extended Access Data High. The most significant byte of data to be written to extended memory is written here before the extended write begins. The most significant byte of data read from extended memory is available here after the extended read is complete. CelXpres T8207 ATM Interconnect Description Description ...

Page 88

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access Registers 30h—37h Table 40. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h) Name Bit Pos. Type Reset ext_a[25 Reserved 7:1 RO Table 41. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h) Name Bit Pos ...

Page 89

... Extended Access Data Low. The least significant byte of data to be written to extended memory is written here before the extended write begins. The least significant byte of data read from extended memory is available here after the extended read is complete. CelXpres T8207 ATM Interconnect Description Description ...

Page 90

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.2.3 General-Purpose I/O Control Registers Table 47. GPIO Output Enable (GPIO_OE) (39h) Name Bit Pos. Type GPIO_oe[7:0] 7:0 RW Table 48. GPIO Output Value (GPIO_OV) (3Bh) Name Bit Pos. Type GPIO_out[7:0] 7:0 RW Table 49. GPIO Input Value (GPIO_IV) (3Dh) Name Bit Pos. Type ...

Page 91

... This memory space in direct 02h memory is a shadow of the control cell transmit 03h extended memory. A control cell to be transmitted 04h should be written to this direct memory space. 05h 06h 07h 08h 09h . . . 36h 37h CelXpres T8207 ATM Interconnect Description Description 91 ...

Page 92

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.2.5 Multicast Memories Table 52. PHY Port 0 and Control Cells Multicast Direct Memory (PP0MDM) (E0h to FFh) The PHY port 0 and control cells multicast memory may also be accessed from extended memory (see Table 122). Name multicast_receive_enable[15:0] multicast_receive_enable[31:16] multicast_receive_enable[47:32] ...

Page 93

... Advance Data Sheet September 2001 14 Registers (continued) 14.3 Extended Memory Registers The CelXpres T8207’s extended memory registers are mapped into three major blocks: the main registers, the UTOPIA registers, and the SDRAM registers. 14.3.1 Main Registers Table 53. Main Configuration 1 (MCF1) (0100h) Name Bit Pos ...

Page 94

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 54. Main Interrupt Status 1 (MIS1) (0102h) Name Bit Pos. Type cb_wc_miss 0 ROL cb_rc_miss 1 ROL cb_fs_miss 2 ROL BIP8_err 3 ROL ctrl_cell_ack 4 ROL ctrl_cell_nack 5 ROL cb_grnt_to 6 ROL ctrl_cell_sent 7 ROL ctrl_cell_av 8 ROL cb_rh_crc_err 9 ROL rx_prty_err 10 ROL soc_err 11 ROL Reserved ...

Page 95

... Start of Cell Error Interrupt Enable. An interrupt is generated if this bit and the corresponding status bit are set. The interrupt is gen- erated until this bit or the corresponding status bit is reset. 0 Reserved. CelXpres T8207 ATM Interconnect 95 ...

Page 96

... These bits are meaningful only when the T8207 generates the TX UTOPIA clock Reserved. Program to ‘0.’ UTOPIA Clock Enable. If this bit is ‘1,’ the T8207 gener- ates the TX UTOPIA clock on the u_txclk pin. If this bit is ‘0,’ the u_txclk pin is configured as an input Reserved. Advance Data Sheet ...

Page 97

... These bits are meaningful only when the T8207 generates the RX UTOPIA clock Reserved. Program to ‘0.’ UTOPIA Clock Enable. If this bit is ‘1,’ the T8207 gener- ates the RX UTOPIA clock on the u_rxclk pin. If this bit is ‘0,’ the u_rxclk pin is configured as an input Reserved. CelXpres T8207 ...

Page 98

... If ‘0,’ cells are not accepted. 1 Slave Enable. If this bit is ‘1,’ the T8207 is configured as a slave in shared UTOPIA mode. The default value of this bit is ‘1.’ Clear this bit if shared UTOPIA is not used. For shared UTOPIA, only one of the two devices may have this bit cleared. Dynamically changing this bit will cause cell loss. When this bit is ‘ ...

Page 99

... RX UTOPIA FIFO is considered full considered full when four cells are stored in it that have not yet been read and processed by the T8207. This bit is valid when the RX UTOPIA is in ATM mode. When this bit is cleared to ‘0,’ the rx_enb* signal is not deasserted even if the RX UTOPIA FIFO is considered full ...

Page 100

... HEC value, and a value of FFh will invert the HEC value. 0 Address Match. These bits represent the UTOPIA address of the T8207 in level 2 UTOPIA multi-PHY mode. These bits are only used when the T8207 is configured as a PHY. 0 Reserved. ...

Page 101

... PHY ports of 32 possible ports, where the most significant bit is port 31 and the least significant bit is port 16. If the corresponding bit is ‘1,’ cells will be received on the desig- nated UTOPIA port. This register is ignored if the T8207_sel bit in the main configuration 2 register equals ‘0.’ Type ...

Page 102

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 66. Extended LUT Control (ELUTCN) (0120h) Name Bit Pos. Type Reset spc_cell_cnt_sel0 0 spc_cell_cnt_sel1 1 spc_cell_cnt_sel2 2 spc_cell_cnt_sel3 3 spc_cell_cnt_sel4 4 spc_cell_cnt_sel5 5 spc_cell_cnt_sel6 6 spc_cell_cnt_sel7 7 spc_cell_cnt_sel8 8 spc_cell_cnt_sel9 9 spc_cell_cnt_sel10 10 spc_cell_cnt_sel11 11 spc_cell_cnt_sel12 12 spc_cell_cnt_sel13 13 spc_cell_cnt_sel14 14 spc_cell_cnt_sel15 15 102 RW 0 Special Cell Count Select 0. When this bit is ‘1,’ cells, whose four least significant bits of their header are “ ...

Page 103

... RAM or the cell bus may be insuffi- cient. An interrupt is generated if the corresponding enable bit is set. ROL 0 Control Cell RX FIFO Overrun. This bit is set when the control cell RX FIFO overflows. An interrupt is generated if the corresponding enable bit is set Reserved. CelXpres T8207 ATM Interconnect Description Description 103 ...

Page 104

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 69. Main Interrupt Enable 2 (MIE2) (0134h) Name Bit Pos. lb_cell_lost_ie 0 Reserved 1 cb_in_fifo_ovrn_ie 2 tx_phy_fifo_ovrn_ie 3 cell_clp1_dis_ie 4 rx_utopia_fifo_ovrn_ie 5 cntl_cell_rx_fifo_ovrn_ie 6 Reserved 15:7 104 Type Reset RW 0 Loopback Cell Lost Interrupt Enable. An interrupt is generated if this bit and the corresponding status bit are set ...

Page 105

... A cell is considered mis- routed if its A and I bits are “00,” if its VCI is out of range the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in the incoming cell header are not all zero. CelXpres T8207 ATM Interconnect Description Description ...

Page 106

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.3.2 UTOPIA Registers Table 74. HEC Interrupt Status 1 (HIS1) (0302h) Name Bit Pos. Type hec_err[31:16] 15:0 RW Table 75. HEC Interrupt Enable 1 (HIE1) (0304h) Name Bit Pos. Type hec_err_ie[31:16] 15:0 RW Table 76. HEC Interrupt Status (HIS) (0306h) Name Bit Pos. Type hec_err[15:0] ...

Page 107

... Address 0320h LUT 8 Configuration/Status 0322h LUT 9 Configuration/Status 0324h LUT 10 Configuration/Status 0326h LUT 11 Configuration/Status 0328h LUT 12 Configuration/Status 032Ah LUT 13 Configuration/Status 032Ch LUT 14 Configuration/Status 032Eh LUT 15 Configuration/Status CelXpres T8207 ATM Interconnect Description Register Address 0330h 0332h 0334h 0336h 0338h 033Ah 033Ch 033Eh 107 ...

Page 108

... RW 0 Master Queue Indication [47:32]. Each bit in this field rep- resents one of 16 queues from the 64 queues in the T8207 device, where the least significant bit is queue 32, and the most significant bit is queue 47. These bits must be set if 64 queues are used. This register is ignored if the T8207_sel bit in the main configuration 2 register equals ‘ ...

Page 109

... RW 0 Master Queue Indication [31:16]. Each bit in this field rep- resents one of 16 queues from the 64 queues in the T8207 device, where the least significant bit is queue 16 and most significant bit is queue 31. These bits indicate which queues in the device are enabled for shared UTOPIA mode. If the associated bit is ‘ ...

Page 110

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 84. Slave Queue 0 (SQ0) (016Ch) Name Bit Pos. Type slav_queue_in[31:16] 15:0 Table 85. Slave Queue 1 (SQ1) (016Eh) Name Bit Pos. Type slav_queue_in[15:0] 15:0 110 Reset RW 0 Slave Queue Indication [31:16]. The bits in this register are used only in shared UTOPIA mode, and only 32 queues are supported in shared UTOPIA mode ...

Page 111

... If the bit is set to ‘1,’ the corresponding queue is assigned to the odd-numbered port. For 32 PHY ports, if the device is config- ured in normal 32-port mode, as described in Section 9.2.2, Out- going ATM Mode (Cells Sent by T8207), and in Section 11.4, Queuing, this register is programmed to “1010101010101010.” With this setting, PHY port 24 is assigned queues 48 and 50, PHY ...

Page 112

... If the bit is set to ‘1,’ the corresponding queue is assigned to the odd-numbered port. For 32 PHY ports, if the device is configured in normal 32-port mode, as described in Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207), and in Section 11.4, Queuing, this register is programmed to “1010101010101010.” With this setting, PHY port 16 is assigned ...

Page 113

... PHY port 10 is assigned queues 20 and 22, PHY port 11 is assigned queues 21 and 23, and so on. For the special case of sixteen ports, if the T8207_sel bit is set, these bits are ignored, and each port is assigned all four queues in the group. PHY 0 is assigned queue group 0, or queues and 3, PHY 1 is assigned queue group 1, or queues and 7, and so on ...

Page 114

... PHY port 3 is assigned queues 5 and 7, and so on. For the special case of sixteen ports, if the T8207_sel bit is set, these bits are ignored, and each port is assigned all four queues in the group. PHY 0 is assigned queue group 0, or queues and 3, PHY 1 is assigned queue group 1, or queues and 7, and so on ...

Page 115

... The value, “110000,” special case and may be used to force the value of this bit to ‘0.’ If this bit is forced to zero, the bit position in the resultant pointer is always ‘0’ and is not extracted from the received cell. 0 Reserved. CelXpres T8207 ATM Interconnect Description 115 ...

Page 116

... The mphy3_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this port group address bit. These bits are ignored when the T8207_sel bit equals ‘0.’ These bits must be programmed if the T8207_sel bit in the main configuration 2 register equals ‘1.’ X Multi-PHY 0 Select [5:0] ...

Page 117

... If this bit is forced to zero, the bit position in the resultant pointer is always ‘0’ and is not extracted from the received cell. 0 Reserved. CelXpres T8207 ATM Interconnect Description 117 ...

Page 118

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 93. PPD Information 1 (PPDI1) (0206h) Name Bit Pos. Type Reset ppd_pnt12_sel[5:0] 5:0 ppd_en_sel[5:0] 11:6 Reserved 15:12 118 RW X PPD Pointer 12 Select. The ppd_pnt12_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tan- dem routing header is used as this offset bit ...

Page 119

... The value, “110000,” special case and may be used to force the value of this bit to ‘0.’ If this bit is forced to zero, the bit position in the resultant pointer is always ‘0’ and is not extracted from the received cell Reserved. CelXpres T8207 ATM Interconnect Description 119 ...

Page 120

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 95. PPD Information 3 (PPDI3) (020Ah) Name Bit Pos. ppd_pnt8_sel[5:0] 5:0 ppd_pnt9_sel[5:0] 11:6 Reserved 15:12 120 Type Reset RW X PPD Pointer 8 Select. The ppd_pnt8_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit ...

Page 121

... The value, “110000,” special case and may be used to force the value of this bit to ‘0.’ If this bit is forced to zero, the bit position in the resultant pointer is always ‘0’ and is not extracted from the received cell Reserved. CelXpres T8207 ATM Interconnect Description 121 ...

Page 122

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 97. PPD Information 5 (PPDI5) (020Eh) Name Bit Pos. Type Reset ppd_pnt4_sel[5:0] 5:0 ppd_pnt5_sel[5:0] 11:6 Reserved 15:12 122 RW X PPD Pointer 4 Select. The ppd_pnt4_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit ...

Page 123

... The value, “110000,” special case and may be used to force the value of this bit to ‘0.’ If this bit is forced to zero, the bit position in the resultant pointer is always ‘0’ and is not extracted from the received cell Reserved. CelXpres T8207 ATM Interconnect Description 123 ...

Page 124

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 99. PPD Information 7 (PPDI7) (0212h) Name Bit Pos. Type ppd_pnt0_sel[5:0] 5:0 RW ppd_pnt1_sel[5:0] 11:6 RW Reserved 15:12 RO Table 100. PPD Memory Write (PPDMW) (0418h) Name Bit Pos. Type write_pul 0 RW write_val 1 RW write_addr 14:2 RW Reserved 15 RO 124 Reset X PPD Pointer 0 Select. ...

Page 125

... PHY Port 26 Transmit Count 0 062Ch PHY Port 27 Transmit Count 0 0630h PHY Port 28 Transmit Count 0 0634h PHY Port 29 Transmit Count 0 0638h PHY Port 30 Transmit Count 0 063Ch PHY Port 31 Transmit Count 0 CelXpres T8207 ATM Interconnect Description Base Address 0640h 0644h 0648h 064Ch 0650h 0654h 0658h ...

Page 126

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.3.2.3 RX UTOPIA Monitoring Table 102. PHY Port X Receive Count Structure (PPXRXCNT) (0700h to 07F8h) Name Offset Bit Pos. in_cnt_phyX[31:16] 00h 15:0 in_cnt_phyX[15:0] 02h 15:0 The letter X in the data structure name and in the bit names represents the values 0 through 31 for the 32 PHY ports ...

Page 127

... Structure Name 0704h LUT 8 configuration 1 070Ch LUT 9 configuration 1 0714h LUT 10 configuration 1 071Ch LUT 11 configuration 1 0724h LUT 12 configuration 1 072Ch LUT 13 configuration 1 0734h LUT 14 configuration 1 073Ch LUT 15 configuration 1 CelXpres T8207 ATM Interconnect Description Base Address 0744h 074Ch 0754h 075Ch 0764h 076Ch 0774h 077Ch 127 ...

Page 128

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.3.3 SDRAM Registers Table 104. SDRAM Control (SCT) (0400h) Name Bit Pos. Type sdram_en 0 RW gen_man_acc 1 WO Reserved 14:2 RO Reserved 15 RW Table 105. SDRAM Interrupt Status (SIS) (0402h) Name Bit Pos. Type ref_late 0 ROL crc8_err_even 1 ROL crc8_err_odd ...

Page 129

... The minimum time from the refresh command to any other command is 15 clock cycles. “00” clock cycles “01” = reserved “10” clock cycles “11” clock cycles 0 Reserved. CelXpres T8207 ATM Interconnect Description 129 ...

Page 130

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 108. Refresh (RFRSH) (0410h) Name Bit Pos. Type ref_cnt 15:0 RW Table 109. Refresh Lateness (RFRSHL) (0412h) Name Bit Pos. Type late_lim 15:0 RW Table 110. Idle State 1 (IS1) (0420h) Name Bit Pos. Type cas_idle 0 RW ras_idle 1 RW ...

Page 131

... RO 0 Reserved. Reset RW 0 SDRAM Address Manual Value. This is the value that will be placed on the sd_a[11:0] pins for one clock cycle when the gen_man_acc bit is written to ‘1.’ Reserved. CelXpres T8207 ATM Interconnect Description Description 131 ...

Page 132

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 114. SDRAM Interrupt Service Request 4 (SISR4) (0438h) Name Bit Pos. Type queue_serv[63:48] 15:0 Table 115. SDRAM Interrupt Service Request 3 (SISR3) (043Ah) Name Bit Pos. Type queue_serv[47:32] 15:0 Table 116. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) Name Bit Pos ...

Page 133

... The interrupt is generated until this bit or the corre- sponding status bit is reset Queue X Overrun Interrupt Enable. An interrupt is gener- ated if this bit and the corresponding status bit are set. The interrupt is generated until this bit or the corresponding sta- tus bit is reset. CelXpres T8207 ATM Interconnect Description 133 ...

Page 134

... Queue 29 (Q29) Queue 14 (Q14) 045Ch Queue 30 (Q30) Queue 15 (Q15) 045Eh Queue 31 (Q31) Note: When the T8207_sel bit = 0, queues 32—63 are disabled (default). 134 Type Reset RW 0 Queue X Empty Interrupt Enable. An interrupt is generated if this bit and the corresponding status bit are set. The interrupt is generated until this bit or the corresponding status bit is reset ...

Page 135

... CLP Fill for Queue X [8:6]. These bits with clp_fillX[24:9] determine the queue’s fill level in cells (64 bytes) where incoming cells with their CLP bit set will be discarded. The incoming cell is dropped at this fill level only when the queueX_clp_en bit is ‘1.’ RO Reserved. CelXpres T8207 ATM Interconnect Description 135 ...

Page 136

... CelXpres T8207 ATM Interconnect 14 Registers (continued) Table 119. Queue X Definition Structure (QXDEF) (2000h to 27E0h) (continued) Name Offset Bit Pos. The letter X in the data structure name and in the bit names represents the values of 0 through 63 for the 64 queues shown below. Structure Name ...

Page 137

... Reset RW X These 56 bytes are the cell routing header, the tandem rout- ing header, and the control cell to be transmitted onto the cell bus. A control cell to be transmitted may be written to this extended memory space. CelXpres T8207 ATM Interconnect Description Description 137 ...

Page 138

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.3.4.2 Multicast Number Memories Table 122. PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) (0C00h to 0C1Eh) The PHY port 0 and control cells multicast memory may also be accessed from direct memory (see Table 52). Name multicast_receive_enable[15:0] multicast_receive_enable[31:16] multicast_receive_enable[47:32] ...

Page 139

... PHY Port 11 Multicast Memory PHY Port 12 Multicast Memory PHY Port 13 Multicast Memory PHY Port 14 Multicast Memory PHY Port 15 Multicast Memory Note: When the T8207_sel bit = ‘0’ multicast memory at address 0D00h—0DECh are ignored. Agere Systems Inc. Offset Type Reset 00h RW ...

Page 140

... CelXpres T8207 ATM Interconnect 14 Registers (continued) 14.3.4.3 PPD State Memory Table 124. PPD Memory (PPDM) (1000h to 13FEh) Name Offset Type Reset word0 00h RW word1 02h word2 04h word3 06h word4 08h word5 0Ah word6 0Ch word7 0Eh . . . . . . word1F9 3F2h word1FA 3F4h word1FB ...

Page 141

... Table 126. SDRAM (SDRAM) (2000000h to 3FFFFFEh) Name Offset Type word0 00h wordFFFFFE 1FFFFFEh Agere Systems Inc. Reset X This memory space is used to access the translation RAM memory. Reset X This memory space is used to access the SDRAM memory. CelXpres T8207 ATM Interconnect Description Description 141 ...

Page 142

... CelXpres T8207 ATM Interconnect 15 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability ...

Page 143

... Table 131. External Clock Requirements Parameter Frequency Maximum Rise or Fall Time Duty Cycle The frequency of the T8207’s main clock (mclk) is derived from the clock at the xtalin input (pclk). See Section 5, PLL Configuration, for more information on these clocks. Agere Systems Inc. Value 5 MHz to 40 MHz ...

Page 144

... CelXpres T8207 ATM Interconnect 18 Electrical Requirements and Characteristics 18.2 dc Electrical Characteristics The following conditions apply except where noted: T Table 132. dc Electrical Characteristics Parameter Supply Current Input Voltage (TTL): Low High Input Voltage (TTL 5 V tolerant): Low High Input Voltage (GTL+): Low High ...

Page 145

... Low — — — — — — 0.8 V 4.0 ns 0.8 V 4.0 ns Rise Time (Max) Fall Time (Max) 1.0 ns 1.0 ns 2.0 ns 2.0 ns 2.0 ns 2.0 ns CelXpres T8207 ATM Interconnect Fall Time Pulse Width (Min) (Max) High Low — 6.06 ns 6.06 ns — 6.06 ns 6. Pulse Width (Min) ...

Page 146

... CelXpres T8207 ATM Interconnect 19 Timing Requirements 19.1 Microprocessor Interface Timing For access time information, see Section 6.3.2, CelXpres T8207 Access Performance. 1 WRITE_ACCESS_ACTIVE A[7:0] D[7:0] 2 RDY_DTACK* 1. write_access_active is the logical OR function of sel* and wr*_ds*. 2. Load is 15 pF. Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. ...

Page 147

... Rising Edge to read_access_active Falling Edge 1. See access times in Table 10. Note: The term pclkp in the table represents the period of pclk in ns. Agere Systems Inc. (continued) Parameter 1 Parameter 1 CelXpres T8207 ATM Interconnect Min Typ Max — — pclkp – — ...

Page 148

... CelXpres T8207 ATM Interconnect 19 Timing Requirements 1 WRITE_ACCESS_ACTIVE A[7:0] D[7:0] 2 RDY_DTACK* 1. write_access_active is the logical OR function of sel*, wr*_ds*, and rd*_wr*. 2. Load is 50 pF. Notes: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the write_access_active signals. ...

Page 149

... Rising Edge to read_access_active Falling Edge 1. See access times in Table 10. Note: The term pclkp in the table represents the period of pclk in ns. Agere Systems Inc. (continued) Parameter Parameter CelXpres T8207 ATM Interconnect Min Typ Max — — pclkp – — ...

Page 150

... CelXpres T8207 ATM Interconnect 19 Timing Requirements 1 WRITE_ACCESS_ACTIVE A[0]/ALE D[7:0] 2 RDY_DTACK* 1. write_access_active is the logical OR function of sel* and wr*_ds*. 2. Load is 50 pF. Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. Figure 25. Multiplexed Intel Mode Write Access Timing ...

Page 151

... Rising Edge to read_access_active Falling Edge 1. See access times in Table 10. Note: The term pclkp in the table represents the period of pclk in ns. Agere Systems Inc. (continued) Parameter 1 Parameter 1 CelXpres T8207 ATM Interconnect Min Typ Max 5 — — — — pclkp – — ...

Page 152

... CelXpres T8207 ATM Interconnect 19 Timing Requirements 19.2 UTOPIA Timing Table 141. TX UTOPIA Timing (70 pF Load on Outputs) u_txclk Frequency u_txclk Duty Cycle Output Delay from u_txclk, Applies to the Following Signals: u_txaddr[4:0] u_txdata[7:0] u_txsoc u_txprty u_txenb*[3:0] u_txclav[0], u_shr_o Input Setup Time to u_txclk, Applies to the Following Signals: ...

Page 153

... Figure 27. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3) TR_A[17:0] & TR_CS*[1:0] TR_WE* TR_OE* TR_D[7:0] Note load on outputs. Figure 28. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3) Agere Systems Inc. (continued CelXpres T8207 ATM Interconnect t4 t3 5-7795bF 5-7796aF 153 ...

Page 154

... CelXpres T8207 ATM Interconnect 19 Timing Requirements The term mclkp in Tables 143, 144, 145, and 146, represents the period of mclk in ns. Table 143. External LUT Memory Read Timing (cyc_per_acc = 2) Symbol Parameter t1 tr_oe* Low to tr_d[7:0] Driven by SRAM Chip t2 tr_a[17:0] & tr_cs*[1:0] Valid to tr_d[7:0] Valid ...

Page 155

... Input Setup to cb_rc* Falling Edge t4 Input Hold from cb_rc* Falling Edge t5 cb_wc* Falling Edge to Output Invalid 1. Pin loading = 25 pF. Agere Systems Inc. (continued Figure 29. Cell Bus Timing Parameter 1 1 CelXpres T8207 ATM Interconnect t5 t4 5-7797bF Min Typ Max Unit 1.5 — — — ...

Page 156

... Timing Requirements 19.5 SDRAM Interface Timing SD_CLK* SD_RAS* SD_CAS* SD_WE* SD_BS[1:0] SD_A[11:0] SD_D[15:0] (SOURCED BY T8207) SD_D[15:0] (SAMPLED BY T8207) Note load on outputs. Table 148. SDRAM Interface Timing Symbol t1 sd_clk Rising to Outputs Valid t2 sd_clk Rising to Outputs Invalid t3 sd_d[15:0] Input Setup to sd_clk Rising Edge t4 ...

Page 157

... CENTER ARRAY E FOR THERMAL D ENHANCEMENT BALL CORNER Agere Systems Inc. 27.00 0.20 +0.70 24.00 –0.00 1.17 0.06 SOLDER BALL 19 SPACES @ 1.27 = 24. CelXpres T8207 ATM Interconnect +0.70 24.00 –0.00 27.00 0.20 0.05 2.33 0.21 SEATING PLANE 0.20 0.75 0.15 19 SPACES @ 1.27 = 24. 5-4406.c 157 ...

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... CelXpres T8207 ATM Interconnect 21 Ordering Information Part Number T-8207---BAL-DB T-8207---BAL-DT Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. Transwitch and CellBus are registered trademarks of Transwitch Corp. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www ...