T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 14
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T8207-BAL-DT
Manufacturer Part Number
T8207-BAL-DT
Description
CelXpres ATM interconnect. Dry-bagget, tape & reel .
Manufacturer
Agere Systems, Inc.
Datasheet
1.T8207-BAL-DT.pdf
(158 pages)
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CelXpres T8207
ATM Interconnect
2
Table 2. Cell Bus Pins
14
cb_vref_vss
cb_disable*
cb_d*[31:0]
Symbol
cb_ack*
arb_en*
ua*[4:0]
cb_vref
cb_wc*
cb_iref
cb_rc*
cb_fs*
Pin Description
B5, C6, D7, A5,
B6, C7, A6, B7,
A7, C8, B8, A8,
D9, C9, B9, A9,
B18, B17, C17,
A12, B12, C12,
D12, A13, B13,
C13, A14, B14,
C14, A15, B15,
A11, C11, B11,
D16, A18
Ball
D14
A10
B10
C15
B16
A17
C16
D10
C10
A4
(continued)
Reset
Value
—
—
—
—
—
—
—
—
Z
Z
Z
Type
I/O
I/O
I/O
—
I
I
I
I
I
I
I
Unit Address Lines (Active-Low). Address assigned to
device for cell bus identification. TTL compatible input, 5 V
tolerant.
Cell Bus Data Lines (Active-Low). GTL+ I/O.
Cell Bus Write Clock (Active-Low). Uses falling edge to
output data on cell bus. Write and read clocks have the
same frequency but different phase. GTL+ input.
Cell Bus Read Clock (Active-Low). Uses falling edge to
latch data from cell bus. Write and read clocks have the
same frequency but different phase. GTL+ input.
Cell Bus Frame Sync (Active-Low). GTL+ I/O.
Cell Bus Acknowledge Signal (Active-Low). Driven low
on cycle 0 of the following frame when a valid cell is
received from the cell bus. This signal is not driven for
broadcast or multicast cells. GTL+ I/O.
Cell Bus Arbiter Enable (Active-Low). Cell bus arbiter
enable. Only one device on the cell bus may be configured
as arbiter. TTL-compatible input, 5 V tolerant. This pin has
an internal 50 k pull-up resistor.
Cell Bus Disable (Active-Low). CMOS input that 3-states
all GTL+ outputs when low, but GTL+ buffer inputs are
active. This pin has an internal 50 k
Cell Bus Current Reference. Precision current reference
for GTL+ buffers. A 1 k , 1% resistor must be connected
between this pin and GND.
Cell Bus Voltage Reference. GTL+ buffer threshold voltage
reference (1.0 V typical). This voltage reference is 2/3 V
created using a voltage divider of three 1 k , 1% resistors
between V
Cell Bus Voltage Reference Ground.
TT
and cb_vref_vss.
Name/Description
Advance Data Sheet
pull-up resistor.
September 2001
Agere Systems Inc.
TT
,
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