T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 130

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

CelXpres T8207
ATM Interconnect
14 Registers
Table 108. Refresh (RFRSH) (0410h)
Table 109. Refresh Lateness (RFRSHL) (0412h)
Table 110. Idle State 1 (IS1) (0420h)
Table 111. Idle State 2 (IS2) (0422h)
130
addr_idle[11:0]
bs_idle[1:0]
Reserved
Reserved
cas_idle
ras_idle
late_lim
we_idle
ref_cnt
Name
Name
Name
Name
Bit Pos. Type
Bit Pos. Type
Bit Pos. Type
Bit Pos. Type
(continued)
15:12
15:0
15:0
15:5
11:0
4:3
0
1
2
RW
RW
RW
RW
RW
RW
RW
RO
RO
Reset
0400h Refresh Count. These bits are used to program the refresh cycle in
Reset
0400h Lateness Limit. These bits are used to program how late a refresh
Reset
Reset
3h
1
1
1
0
0
0
SDRAM clock cycles. The number of clock cycles programmed in
this register should be less than one half the worst-case refresh
period.
cycle may occur. This limit is in refresh cycles. When this limit is
reached, the ref_late status bit will be set.
SDRAM CAS Idle Value. This is the value that will be placed on the
sd_cas* pin while the SDRAM is idle (sdram_en = ‘0’).
SDRAM RAS Idle Value. This is the value that will be placed on the
sd_ras* pin while the SDRAM is idle (sdram_en = ‘0’).
SDRAM Write Enable Idle Value. This is the value that will be
placed on the sd_we* pin while the SDRAM is idle (sdram_en = ‘0’).
SDRAM Bank Select Idle Value. This is the value that will be
placed on the sd_bs[1:0] pins while the SDRAM is idle
(sdram_en = ‘0’).
Reserved.
SDRAM Address Idle Value. This is the value that will be placed on
the sd_a[11:0] pins while the SDRAM is idle (sdram_en = ‘0’).
Reserved.
Description
Description
Description
Description
Advance Data Sheet
September 2001
Agere Systems Inc.