T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 127

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
Table 103. LUT X Configuration 1 Structure (LUTXCF1) (0704h to 077Ch)
The letter X in the data structure name and in the bit names represents the values 0 through 15 for the 16 look-up
table configurations. The base addresses of the 16 data structures are shown below.
lutX_vpi_mask
lutX_vpi_base
lutX_vpi_chk
lutX_uni_en
Reserved
Name
LUT 0 configuration 1
LUT 1 configuration 1
LUT 2 configuration 1
LUT 3 configuration 1
LUT 4 configuration 1
LUT 5 configuration 1
LUT 6 configuration 1
LUT 7 configuration 1
Structure Name
(continued)
Offset
00h
02h
Bit Pos.
15:14
15:0
11:0
12
13
Type
Base Address
RW
070Ch
071Ch
072Ch
073Ch
0704h
0714h
0724h
0734h
Reset
X
LUT X VPI Base Address. These bits define bits 3
through 18 of the VPI base address offset in look-up
table X. The offset may be a maximum of 19 bits. If
16-byte records are used, the least significant bit of this
word is ignored.
Note: When 16 or less PHY ports are used, each PHY
LUT X VPI Mask. This 12-bit field is used to mask the
incoming VPI bits. If a bit in the field is set to ‘1,’ the
corresponding incoming VPI bit will be used to address
the VPI record in the look-up table. All other incoming
VPI bits will be ignored.
LUT X VPI Check. If this bit is set to ‘1,’ the unused
incoming VPI bits must be ‘0,’ or the cell will be
counted as misrouted. Unused bits are bits whose cor-
responding lutX_vpi_mask bit equal zero.
LUT X User Network Interface (UNI) Enable. If this
bit is set to ‘1,’ the port is identified as UNI, and the
GFC field of the cell header will not be used in the look-
up table. If this bit is ‘0,’ the port is identified as NNI.
Reserved.
port has its own look-up table memory space.
For 16 or less PHY ports, PHY port 0 uses
LUT 0 memory space, PHY port 1 uses LUT 1
memory space, and so on. When greater than
16 PHY ports are used, even and odd PHY ports
must share the look-up memory space. For
greater than 16 PHY ports, PHY ports 0 and 1
use LUT 0 memory space, PHY ports 2 and 3
use LUT 1 memory space, PHY ports 4 and 5
use LUT 2 memory space, and so on.
LUT 10 configuration 1
LUT 12 configuration 1
LUT 13 configuration 1
LUT 14 configuration 1
LUT 15 configuration 1
LUT 11 configuration 1
LUT 8 configuration 1
LUT 9 configuration 1
Structure Name
Description
ATM Interconnect
CelXpres T8207
Base Address
074Ch
075Ch
076Ch
077Ch
0744h
0754h
0764h
0774h
127