T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 93

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

Advance Data Sheet
September 2001
Agere Systems Inc.
14 Registers
14.3 Extended Memory Registers
The CelXpres T8207’s extended memory registers are mapped into three major blocks: the main registers, the
UTOPIA registers, and the SDRAM registers.
14.3.1 Main Registers
Table 53. Main Configuration 1 (MCF1) (0100h)
tx_utopia_hi_z
sdram_bypass
tram_qnty_sel
sp_utopia_sel
Reserved
tram_size
Reserved
Name
phyen
(continued)
Bit Pos. Type
14:13
7:0
10
12
15
11
8
9
RW
RW
RW
RW
RW
RW
RW
RO
Reset
00h
0
0
1
0
1
0
0
Reserved.
Transmit UTOPIA High Impedance. When the device is in ATM
and shared UTOPIA mode, this bit must be cleared to ‘0’:
When the device is in ATM and nonshared UTOPIA mode and this
bit is cleared to ‘0,’ the u_txdata[7:0] and u_txprty outputs go high
impedance when not active.
When the device is in PHY mode and this bit is cleared to ‘0,’ the
u_txsoc, u_txdata[7:0], and u_txprty outputs go high impedance
when not active. If the device acts as one of the multi-PHY
devices, then this bit must be cleared to ‘0.’
When this bit is set to ‘1,’ the u_txsoc, u_txdata[7:0], and u_txprty
outputs never go high impedance.
SDRAM Bypass. When this bit is ‘1,’ the T8207 will not use
SDRAM and will use only internal memory to buffer cell bus data.
Clear this bit to enable the SDRAM interface. Only queue 0 is used
when the SDRAM is bypassed.
PHY Enable. When this bit is ‘1,’ the UTOPIA bus is configured for
ATM mode. When ‘0,’ the UTOPIA bus is configured for PHY
mode.
Translation RAM Quantity Select. When two external SRAM
devices are used, this bit should be set. When this bit is cleared,
only one external SRAM will be accessed using tr_cs*[0].
Special UTOPIA Mode Select. When this bit is ‘1,’ the T8207 will
send 53-byte cells on the UTOPIA bus. When it is ‘0,’ the 55-byte
UTOPIA mode is selected, and the tandem routing header bytes
will be appended to the beginning of each cell.
Translation RAM Size. These bits identify the size of the external
SRAM used for the look-up table RAM.
“00” = 32K bytes
“01” = 64K bytes
“10” = 128K bytes
“11” = 256K bytes
Reserved. Program to ‘0.’
For the slave device, the u_txsoc output will always be high
impedance while the u_txdata[7:0] and u_txprty outputs go high
impedance when not active.
For the master device, the u_txdata[7:0] and u_txprty outputs go
high impedance when not active.
Description
ATM Interconnect
CelXpres T8207
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