T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 54

• Manufacturer Part Number: T8207-BAL-DT
• Description: CelXpres ATM interconnect. Dry-bagget, tape & reel .
• Manufacturer: Agere Systems, Inc.

CelXpres T8207
Advance Data Sheet
ATM Interconnect
September 2001
10
Cell Bus Interface
10.1 General Architecture
The high bandwidth, 32-bit cell bus is used to interconnect T8207 devices. Up to 32 devices may be connected to
the bus, and cell exchange may occur between any of these devices. Each cell bus frame is 16 clock cycles, and
during these 16 cycles, one cell is transmitted. The T8207 is designed to operate with a maximum cell bus fre-
quency of 66 MHz, which translates to a cell bandwidth of 1.7 Gbits/s. The maximum achievable frequency for a
given bus implementation is dependent on loading and other design considerations.
In addition to the 32 bits of data, the cell bus uses four additional control signals. The four signals include a read
clock, a write clock, a frame synchronization signal, and an acknowledge signal.
The read and write clocks (cb_rc* and cb_wc* pins, respectively) establish the timing for reading and writing cells
on the bus and are generated from an external clock source. The read clock is used to read the cell from the cell
bus, and the write clock is used to write the cell to the cell bus. Because all devices on the cell bus read and write
on the same clock edge, the write clock is delayed slightly, relative to the read clock, to ensure sufficient data hold
time.
The active-low frame sync (cb_fs*) is generated by the bus arbiter and indicates the first cycle of the cell bus frame
in 16 user mode or the first cycle of two cell bus frames for 32 user mode. This signal is generated every 16 clock
cycles for 16 user mode or every 32 clock cycles for 32 user mode.
The acknowledge (cb_ack*) signal is used to acknowledge the successful receipt of a cell. This signal is asserted
low during the next request cycle by the T8207 that receives the cell. This signal is not asserted for multicast or
broadcast cells. In the event of an overflow in the control cell RX FIFO, the loopback FIFO, the TX PHY FIFO, or
the cell bus input FIFO, the acknowledge signal will assert low. In the case of an overflow, this signal will not assert
low for multicast and broadcast cells.
When cb_disable* is asserted, the device can receive data on the cb_d*[31:0] but cannot transmit data. The device
cannot assert the cb_ack* even when a valid cell is received from the cell bus, if cb_disable* is asserted.
Several T8207 devices may reside on the cell bus, but one device must be configured as bus arbiter by clearing
the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low.
The cell bus arbiter receives requests for access to the bus from all resident devices during the first cycle of the cell
bus frame and grants one of these requests during the last cycle of the cell bus frame. Before issuing the grant and
while a cell is transmitted on the cell bus, the arbiter executes its arbitration algorithm to determine the next device
to transmit on the bus. The arbiter also generates the frame synchronization signal. Software shall designate only
one device as cell bus arbiter, at any given time, to ensure proper operation of the bus.
A 5-bit unit address is assigned to each device (up to 32) on the bus. Each device uses this address to request cell
transmission and to identify incoming cells destined for them. Each device is given a unique unit address by indi-
vidually tying each address (ua*[4:0]) input high or low. The unit address inputs are active-low; therefore, a device
with its ua*[4:0] inputs tied to “10000” has address 15. The device makes a cell transmission request by driving the
two assigned bits during the request cycle, which is the first cycle of a frame. For example, device 15 uses bits 30
and 31 of the request cycle as its request bits. (See Section 10.2, Cell Bus Frames.) Also, each device uses its unit
address to determine if a received cell is destined for it. (See Section 10.3, Cell Bus Routing Headers.)
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Agere Systems Inc.